Datasheet

19
21576512f
LTC2157-12/
LTC2156-12/LTC2155-12
APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. The duty cycle
stabilizer is enabled via SPI Register A2 (see Table 3) or
by CS in parallel programming mode.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. In
this case care should be taken to make the clock a 50%
(±5%) duty cycle.
Figure 9. Sinusoidal Encode Drive
DIGITAL OUTPUTS
The digital outputs are double-data rate LVDS signals. Two
data bits are multiplexed and output on each differential
output pair. There are six LVDS output pairs for channel A
(DA0_1
+
/DA0_1
through DA10_11
/DA10_11
+
) and six
pairs for channel B (DB0_1
+
/DB0_1
through DB10_11
/
DB10_11
+
). Overflow (OF
+
/OF
) and the data output clock
(CLKOUT
+
/CLKOUT
) each have an LVDS output pair. Note
that overflow for both channels is multiplexed onto the
OF
+
/OF
output pair.
Figure 10. PECL or LVDS Encode Drive
LTC2157-12
T1
V
DD
21576512 F09
1.2V
10k
50Ω
100Ω
50Ω
0.1µF
0.1µF
T1: MACOM ETC1-1-13
V
DD
LTC2157-12
PECL OR
LVDS INPUT
21576512 F10
1.2V
10k
100Ω
0.1µF
0.1µF
ENC
+
ENC