Datasheet

LTC2157-12/
LTC2156-12/LTC2155-12
16
21576512f
PIN FUNCTIONS
LVDS Outputs
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OF
–
/OF
+
(Pins 22/23): Over/Underflow Digital Output.
OF
+
is high when an overflow or underflow has occurred.
The overflows for channel A and channel B are multiplexed
together.
D
B0_1
–
/D
B0_1
+
to D
B10_11
–
/D
B10_11
+
(Pins 26/27, 28/29,
30/31, 34/35, 36/37, 38/39): Channel B Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (DB0, DB2, DB4,
DB6, DB8, DB10) appear when CLKOUT
+
is low. The odd
data bits (DB1, DB3, DB5, DB7, DB9, DB11) appear when
CLKOUT
+
is high.
CLKOUT
–
/CLKOUT
+
(Pins 40/41): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT
+
. The phase of
CLKOUT
+
can also be delayed relative to the digital outputs
by programming the mode control registers.
D
A0_1
–
/D
A0_1
+
to D
A10_11
–
/D
A10_11
+
(Pins 44/45, 46/47,
50/51, 52/53, 54/55, 56/57): Channel A Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (DA0, DA2, DA4,
DA6, DA8, DA10) appear when CLKOUT
+
is low. The odd
data bits (DA1, DA3, DA5, DA7, DA9, DA11) appear when
CLKOUT
+
is high.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
S/H
V
CM
BUFFER
BUFFER
BUFFER
GND
V
CM
0.1µF
CORRECTION
LOGIC
OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE CONTROL
1.25V
REFERENCE
RANGE
SELECT
CLOCK
ANALOG
INPUT
21576512 F01
DDR
LVDS
DDR
LVDS
V
DD
OV
DD
OGND
CS
CHANNEL A
CHANNEL B
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
SPI
12-BIT
PIPELINED
ADC CORE
ANALOG
INPUT
OV
DD
OGND
V
REF
2.2µF
GND
GND
SENSE
SCK
SDI
PAR/SER
DA10_11
•
•
•
DA0_1
DB10_11
•
•
•
DB0_1