Datasheet

LTC1983-3/LTC1983-5
9
1983fa
problem in the low I
Q
mode, it is necessary to switch the
part in and out of shutdown at the minimum allowable
frequency (refer to Figure 3) for a given output load.
General Layout Considerations
Due to the high switching frequency and high transient
currents produced by the LTC1983, careful board layout is
a must. A clean board layout using a ground plane and
short connections to all capacitors will improve perfor-
mance and ensure proper regulation under all conditions
(refer to Figures 4a and 4b). You will not get advertised
performance with careless layout.
Figure 3
OUTPUT CURRENT (µA)
1
10
100
1000
MAXIMUM SHDN OFF TIME (ms)
1000
1983 F03b
1 10 100
SHDN ON PULSE WIDTH = 200µs
C
OUT
= 10µF
Figure 4a. Recommended Component
Placement for a Single Layer Board
Figure 4b. Recommended Component
Placement for a Double Layer Board
1 V
IN
2 V
OUT
3 C
+
SHDN 6
GND 5
C
–
4
C
OUT
C
FLY
V
IN
: 2.3V TO 5.5V
V
OUT
1983 F04a
C
IN
1 V
IN
2 V
OUT
3 C
+
SHDN 6
GND 5
C
–
4
C
IN
C
OUT
C
FLY
V
OUT
1983 F04b
BOTTOM LAYER TOP LAYER
OPERATIO
U
(Refer to Block Diagram)