Datasheet

14
LTC1967
1967f
100mV to 110mV (+10%) and back (–10%), the step
responses are essentially the same as a standard expo-
nential rise and decay between those two levels. In such
cases, the time constant of the decay will be in between
that of the rising edge and falling edge cases of Figure 10.
Therefore, the worst case is the falling edge response as
it goes to zero, and it can be used as a design guide.
Figure␣ 11 shows the settling accuracy vs settling time for
a variety of averaging capacitor values. If the capacitor
value previously selected (based on error requirements)
gives an acceptable settling time, your design is done.
But with 100µF, the settling time to even 10% is a full 20
seconds, which is a long time to wait. What can be done
about such a design? If the reason for choosing 100µF is
to keep the DC error with a 100mHz input less than 0.1%,
the answer is: not much. The settling time to 1% of 32
seconds is just 3.2 cycles of this extremely low frequency.
Averaging very low frequency signals takes a long time.
However, if the reason for choosing 100µF is to keep the
peak error with a 10Hz input less than 0.1%, there is
another way to achieve that result with a much improved
settling time.
APPLICATIO S I FOR ATIO
WUUU
TIME (SEC)
0
0
OUTPUT (mV)
20
40
60
80
100
120
0.05 0.1 0.15 0.2
1967 F10a
0.25
C
AVE
= 1µF
Figure 10a. LTC1967 Rising Edge with C
AVE
= 1µF
Figure 10b. LTC1967 Falling Edge with C
AVE
= 1µF
Figure 11. Settling Time with One Cap Averaging
TIME (SEC)
0
0
OUTPUT (mV)
20
40
60
80
100
120
0.1 0.2 0.3 0.4
1967 F10b
0.5
C
AVE
= 1µF
SETTLING TIME (SEC)
0.01
0.1
SETTLING ACCURACY (%)
1
10
1100.1 100
1966 F12
C = 0.1µF C = 0.22µF C = 0.47µF C = 1µF C = 2.2µF C = 4.7µF C = 10µF C = 22µF C = 47µF C = 100µF