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LTC1966

1966fb

applicaTions inForMaTion

within the filter. Scaling the buffered topology of Figure 13

is simple because the capacitors are in a 10:1:10 ratio.

Scaling the DC accurate topology of Figure 14 can be done

with standard value capacitors; one decade of scaling is

shown in Table 2.

Table 2. One Decade of Capacitor Scaling for Figure 14 with EIA

Standard Values

AVE

= C

1µF 0.22µF

1.5µF 0.33µF

2.2µF 0.47µF

3.3µF 0.68µF

4.7µF 1µF

6.8µF 1.5µF

Figures 19 and 20 show the settling time versus settling

accuracy for the buffered and DC accurate post filters,

respectively. The different curves represent different scal-

ings of the filters, as indicated by the C

AVE

value. These are

comparable to the curves in Figure 12 (single capacitor

case), with somewhat less settling time for the buffered

post filter, and somewhat more settling time for the DC

accurate post filter. These differences are due to the change

in overall bandwidth as mentioned earlier.

The other difference is the settling behavior of the filters

below the 1% level. Unlike the case of a 1st order filter,

any 3rd order filter can have overshoot and ringing. The

filter designs presented here have minimal overshoot

and ringing, but are somewhat sensitive to component

mismatches. Even the ±12% tolerance of the LTC1966

output impedance can be enough to cause some ringing.

The dashed lines indicate what can happen when ±5%

capacitors and ±1% resistors are used.

Figure 18. Peak Error vs Input Frequency with DC Accurate Post Filter

Figure 17. Peak Error vs Input Frequency with Buffered Post Filter

INPUT FREQUENCY (Hz)

–2.0

PEAK ERROR (%)

–1.6

–1.2

–0.8

–0.4

10 100

1966 F17

–1.8

–1.4

–1.0

–0.6

–0.2

C = 10µF

C = 4.7µF C = 2.2µF C = 1.0µF C = 0.47µF C = 0.22µF

C = 0.1µF