Datasheet

LTC1922-1
21
slower. A linearized SPICE macromodel of the control loop
is very helpful tool to quickly evaluate the frequency
response of various compensation networks.
Polymer Electrolytic (see Figure 12) 1/(2πC
C
R
I
) sets a
low frequency pole. 1/(2πC
C
R
F
) sets the low frequency
zero. The zero frequency should coincide with the worst-
case lowest output pole frequency. The pole frequency
and mid frequency gain (R
F
/R
I
) should be set such so that
the loop crosses over zero dB with a –1 slope at a
frequency lower than (f
SW
/8). Use a bode plot to graphi-
cally display the frequency response. An optional higher
frequency pole set by CP2 and R
f
is used to attenuate
switching frequency noise.
Aluminum Electrolytic (see Figure 12) the goal of this
compensator will be to cross over the output minimum
pole frequency. Set a low frequency pole with C
C
and R
IN
at a frequency that will cross over the loop at the output
pole minimum F, place the zero formed by C
C
and R
f
at the
output pole F.
Synchronous Rectification
The LTC1922-1 produces the precise timing signals nec-
essary to control current doubler secondary side synchro-
nous MOSFETs on OUTE and OUTF. Synchronous rectifi-
ers are used in place of Schottky or Silicon diodes on the
secondary side of the power supply. As MOSFET R
DS(ON)
levels continue to drop, significant efficiency improve-
ments can be realized with synchronous rectification,
provided that the MOSFET switch timing is optimized. An
additional benefit realized with synchronous rectifiers is
bipolar output current capability. These characteristics
improve transient response, particularly overshoot, and
improve ZVS ability at light loads.
Figure 12. Compensation for Polymer Electrolytic
Current Doubler
The current doubler secondary employs two output induc-
tors that equally share the output load current. The trans-
former secondary is not center-tapped. This configuration
provides 2× higher output current capability compared to
similarly sized single output inductor modules, hence the
name. Each output inductor is twice the inductance value
as the equivalent single inductor configuration and the
transformer turns ratio is 1/2 that of a single inductor
secondary. The drive to the inductors is 180 degrees out
of phase which provides partial ripple current cancellation
in the output capacitor(s). Reduced capacitor ripple cur-
rent lowers output voltage ripple and enhances the
capacitors’s reliability. The amount of ripple cancellation
is related to duty cycle (see Figure 13). Although the
current doubler requires an additional inductor, the induc-
tor core volume is proportional to LI
2
, thus the size penalty
is small. The transformer construction is simplified with-
out a center-tap winding and the turns ratio is reduced by
1/2 compared to a conventional full wave rectifier configu-
ration.
Figure 13. Ripple Current Cancellation vs Duty Cycle
Synchronous rectification of the current doubler second-
ary requires two ground referenced N-channel MOSFETs.
The timing of the LTC1922-1 drive signals is shown in the
Timing Diagram. Synchronous rectifier turn-on is inter-
nally delayed by the LTC1922-1 after OUT (C or D)
turn-off—just after the end of a power cycle. Synchronous
rectifier turn-off occurs coincident with OUT (A or B)
turn-off. This gives a passive transition time margin before
+
–
2.5V
R
f
R
L
R
D
ESR
REF
R
I
C
C
C
O
C
P2
V
OUT
COLL
COMP
OPTO
V
OUT
LT1431 OR EQUIVALENT
PRECISION ERROR
AMP AND REFERENCE
OPTIONAL
1922 F12
1
0
0 0.25 0.5
DUTY CYCLE
NORMALIZED
OUTPUT RIPPLE
CURRENT
ATTENUATION
1922 • F13
NOTE: INDUCTOR(S) DUTY CYCLE
IS LIMITED TO 50% WITH CURRENT
DOUBLER PHASE SHIFT CONTROL.
OPERATIO
U