Datasheet

7
LTC1911-1.5/LTC1911-1.8
1911f
transferred to the parallel combination of C1 and C2 is
transferred to the V
OUT
. In this manner, charge is again
transferred from the flying capacitors to the output on
both phases of the clock. As in 2-to-1 mode, charge
current is sourced from GND on phase two of the clock
resulting in increased power efficiency. I
OUT
in 3-to-2
mode equals approximately (3/2)I
IN
.
In 1-to-1 mode (see Figure 1c), switch S1 is always closed
connecting the top plate of C1 to V
OUT
. Switch S2 remains
closed for almost the entire clock period, opening only
briefly at the end of clock phase one. In this manner, V
OUT
is connected to V
IN
through R
A
. The value of R
A
is set by
the regulator control loop which determines the amount of
current transferred to V
OUT
during the on period of S2. The
LTC1911 acts much like a linear regulator in this mode.
Since all of the V
OUT
current is sourced from V
IN
, the
efficiency in 1-to-1 mode is approximately equal to that of
a linear regulator.
Mode Selection
The optimal step-down conversion mode is chosen based
on V
IN
and output load conditions. Two internal compara-
tors are used to select the default step-down mode based
on the input voltage. Each comparator has an adjustable
offset built in that increases (decreases) in proportion to
the increasing (decreasing) output load current. In this
manner, the mode switch point is optimized to provide
peak efficiency over all supply and load conditions. Each
comparator also has built-in hysteresis of about 300mV to
ensure that the LTC1911 does not oscillate between modes
when a transition point is reached.
Soft-Start/Shutdown Operation
The SS/SHDN pin is used to implement both low current
shutdown and soft-start. The soft-start feature limits
inrush currents when the regulator is initially powered up
or taken out of shutdown. Forcing a voltage lower than
0.6V (typ) on the SS/SHDN pin will put the LTC1911 into
shutdown mode. Shutdown mode disables all control
circuitry and forces V
OUT
into a high impedance state. A
2µA pull-up current on the SS/SHDN pin will force the part
into active mode if the pin is left floating or is driven with
an open-drain output that is in a high impedance state. If
the pin is not driven with an open-drain device, it must be
forced to a logic high voltage of 2.2V (min) to ensure
proper V
OUT
regulation. The SS/SHDN pin should not be
driven to a voltage higher than V
IN
. To implement soft-
start, the SS/SHDN pin must be driven with an open-drain
device and a capacitor must be connected from the SS/
SHDN pin to GND. Once the open-drain device is turned
off, the 2µA pull-up current will begin charging the external
soft-start capacitor and force the voltage on the pin to
ramp towards V
IN
. As soon as the shutdown threshold is
reached (0.6V typ), the internal reference voltage that
controls the V
OUT
regulation point will follow the ramp
voltage on the SS/SHDN pin (minus a 0.6V offset to
account for the shutdown threshold) until the reference
reaches its final band gap voltage. This occurs when the
voltage on the SS/SHDN pin reaches approximately 1.9V.
Since the ramp rate on the SS/SHDN pin controls the ramp
rate on V
OUT
, the average inrush current can be controlled
through the selection of C
SS
and C
OUT
. For example, a
APPLICATIO S I FOR ATIO
WUUU
V
IN
V
OUT
C1
R
A
C1
+
C1
–
C2
+
C2
–
S5
φ1
S7
φ1
S4
φ1
S1
φ2
S2
φ2
GND
C2
1911 F01b
S6
φ1
S3
φ2
Figure 1b. Step-Down Charge Transfer in 3-to-2 Mode
V
IN
V
OUT
C1
R
A
C1
+
C1
–
1911 F01c
S2 S1
Figure 1c. Step-Down Charge Transfer in 1-to-1 Mode