Datasheet

LTC1877
9
1877fb
The basic LTC1877 application circuit is shown on the fi rst
page. External component selection is driven by the load
requirement and begins with the selection of L followed
by C
IN
and C
OUT
.
Inductor Value Calculation
The inductor selection will depend on the operating fre-
quency of the LTC1877. The internal nominal frequency is
550kHz, but can be externally synchronized from 400kHz
to 700kHz.
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use of
smaller inductor and capacitor values. However, operating
at a higher frequency generally results in lower effi ciency
because of increased internal gate charge losses.
The inductor value has a direct effect on ripple current.
The ripple current ΔI
L
decreases with higher inductance
or frequency and increases with higher V
IN
or V
OUT
.
ΔI
L
=
1
f
()
L
()
V
OUT
1−
V
OUT
V
IN
⎛
⎝
⎜
⎞
⎠
⎟
(1)
Figure 1. Maximum Output Current vs Input Voltage
Dropout Operation
When the input supply voltage decreases toward the output
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces the
main switch to remain on for more than one cycle until it
reaches 100% duty cycle. The output voltage will then be
determined by the input voltage minus the voltage drop
across the internal P-channel MOSFET and the inductor.
Low Supply Operation
The LTC1877 is designed to operate down to an input supply
voltage of 2.65V although the maximum allowable output
current is reduced at this low voltage. Figure 1 shows the
reduction in the maximum output current as a function of
input voltage for various output voltages.
OPERATION
Another important detail to remember is that at low input
supply voltages, the R
DS(ON)
of the P-channel switch in-
creases. Therefore, the user should calculate the power
dissipation when the LTC1877 is used at 100% duty cycle
with a low input voltage (see Thermal Considerations in
the Applications Information section).
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant-fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current signal
at duty cycles in excess of 40%. As a result, the maximum
inductor peak current is reduced for duty cycles >40%.
This is shown in the decrease of the inductor peak current
as a function of duty cycle graph in Figure 2.
V
IN
(V)
0
MAX OUTPUT CURRENT (mA)
1200
1000
800
600
400
200
0
2
468
1877 F01
10 12
V
OUT
= 2.5V
V
OUT
= 1.5V
V
OUT
= 3.3V
V
OUT
= 5V
L = 10μH
DUTY CYCLE (%)
0
MAXIMUM INDUCTOR PEAK CURRENT (mA)
1100
1000
900
800
700
600
80
1877 F02
20
40
60
100
V
IN
= 5V
Figure 2. Maximum Inductor Peak Current vs Duty Cycle
APPLICATIONS INFORMATION