Datasheet

LTC1877
12
1877fb
this stable operating point the phase comparator output
is high impedance and the fi lter capacitor C
LP
holds the
voltage.
The loop fi lter components C
LP
and R
LP
smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The fi lter
component’s C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF
to 0.01μF. When not synchronized to an external clock,
the internal connection to the V
CO
is disconnected. This
disallows setting the internal oscillator frequency by a DC
voltage on the V
PLL LPF
pin.
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC1877 circuits: V
IN
quiescent current and
I
2
R losses. The V
IN
quiescent current loss dominates the
effi ciency loss at very low load currents, whereas the
I
2
R loss dominates the effi ciency loss at medium to high
load currents. In a typical effi ciency plot, the effi ciency
curve at very low load currents can be misleading since
the actual power lost is of no consequence, as illustrated
in Figure 6.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the Electrical Charac-
teristics section and the internal main switch and syn-
chronous switch gate charge currents. The gate charge
current results from switching the gate capacitance
of the internal power MOSFET switches. Each time
the gate is switched from high to low to high again, a
packet of charge dQ moves from V
IN
to ground. The
resulting dQ/dt is the current out of V
IN
that is typically
larger than the DC bias current. In continuous mode,
I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate
charges of the internal top and bottom switches. Both
the DC bias and gate charge losses are proportional
to V
IN
and thus their effects will be more pronounced
at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current fl ow-
ing through inductor L is chopped between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT)
(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I
2
R losses, simply add
R
SW
to R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative los-
ses and inductor core losses generally account for less
than 2% total additional loss.
LOAD CURRENT (mA)
0.1 1
0.00001
POWER LOST (W)
0.001
1
10 100 1000
1877 F06
0.0001
0.01
0.1
V
OUT
= 1.5V
V
OUT
= 2.5V
V
OUT
= 3.3V
V
IN
= 4.2V
L = 10μH
Burst Mode OPERATION
Figure 6. Power Lost vs Load Current
Thermal Considerations
In most applications the LTC1877 does not dissipate much
heat due to its high effi ciency. But, in applications where the
LTC1877 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
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