Datasheet

13
LTC1875
1875f
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
Where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1875 circuits: supply quiescent currents and
I
2
R losses. The supply quiescent current loss dominates
the efficiency loss at very low load current whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 7.
1. The supply quiescent current is due to two compo-
nents: the DC bias current as given in the Electrical
Characteristics and the internal main switch and syn-
chronous switch gate charge currents. The gate charge
current results from switching the gate capacitance of
the internal power MOSFET switches. Each time the
gate is switched from high to low to high again, a
packet of charge dQ moves from PV
IN
to ground. The
resulting dQ/dt is the current out of PV
IN
that is typically
larger than the DC bias current. In continuous mode,
I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate
charges of the internal top and bottom switches. Both
the DC bias and gate charge losses are proportional to
supply voltage and thus their effects will be more
pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches R
SW
and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into SW pins is a function of both top
and bottom MOSFET R
DS(ON)
and the duty cycle (DC) as
follows:
R
SW
= (R
DS(ON)TOP
)(DC) + R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, MOSFET switching losses and inductor core losses
generally account for less than 2% total additional loss.
Thermal Considerations
In most applications, the LTC1875 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC1875 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW nodes will become high
impedance.
APPLICATIO S I FOR ATIO
WUUU
Figure 7. Power Lost vs Load Current
LOAD CURRENT (mA)
0.001
POWER LOST (W)
0.01
0.1
1
0.1 10 100 1000
1875 F07
0.0001
1
V
IN
= 6V
V
OUT
= 3.3V
L = 6.8µH
Burst Mode
OPERATION