Datasheet

12
LTC1875
1875f
APPLICATIO S I FOR ATIO
WUUU
filter network on the PLL_LPF pin. The relationship be-
tween the voltage on the PLL_LPF pin and operating
frequency is shown in Figure 5. A simplified block diagram
is shown in Figure 6.
If the external frequency (V
SYNC/MODE
) is greater than
550kHz, the center frequency, current is sourced continu-
ously, pulling up the PLL_LPF pin. When the external
frequency is less than 550kHz, current is sunk continu-
ously, pulling down the PLL_LPF pin. If the external and
internal frequencies are the same but exhibit a phase
difference, the current sources turn on for an amount of
time corresponding to the phase difference. Thus the
voltage on the PLL_LPF pin is adjusted until the phase and
frequency of the external and internal oscillators are
identical. At this stable operating point the phase com-
parator output is open and the filter capacitor C
LP
holds the
voltage.
The loop filter components C
LP
and R
LP
smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01µF. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillation frequency by a DC
voltage on the V
PLLLPF
pin.
Figure 5. Relationship Between Oscillator Frequency
and Voltage at PLL_LPF Pin
DIGITAL
PHASE/
FREQUENCY
DETECTOR
SYNC/
MODE
PLL_LPF
2.4V
C
LP
1875 F06
R
LP
VCO
Figure 6. Phase-Locked Loop Block Diagram
Phase-Locked Loop and Frequency Synchronization
The LTC1875 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the MOSFET turn-on to be locked to the rising edge
of an external frequency source. The frequency range of
the voltage-controlled oscillator is 350kHz to 750kHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector will not
lock up on input frequencies close to the harmonics of the
VCO center frequency. The PLL hold-in range ∆f
H
is equal
to the capture range, ∆f
H
= ∆f
C
= ±200kHz.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
V
FB
LTC1875
0.8V ≤ V
OUT
≤ 6V
SGND
R2
1875 F04
R1
Figure 4. Setting the LTC1875 Output Voltage
V
PLLLPF
(V)
0
OSC FREQUECNY (kHz)
1000
900
800
700
600
500
400
300
200
100
0
1875 F05
0.5 1 1.5 2