Datasheet

LTC1871-7
23
18717fd
applicaTions inForMaTion
7. Minimize the capacitance between the SENSE pin
trace and any high frequency switching nodes. The
LTC1871-7 contains an internal leading edge blanking
time of approximately 180ns, which should be adequate
for most applications.
8. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC1871-7 in order
to keep the high impedance FB node short.
Figure 18. LTC1871-7 Boost Converter Suggested Layout
Figure 19. LTC1871-7 Boost Converter Layout Diagram
LTC1871-7
M1
V
IN
1871 F18
V
OUT
SWITCH NODE IS ALSO
THE HEAT SPREADER
FOR L1, M1, D1
L1
R
T
R
S
R
C
C
C
R3
J1
C
IN
C
OUT
C
VCC
R1
R2
PSEUDO-KELVIN
SIGNAL GROUND
CONNECTION
TRUE REMOTE
OUTPUT SENSING
VIAS TO GROUND
PLANE
R4
PIN 1
C
OUT
JUMPER
D1
RUN
I
TH
FB
FREQ
MODE/
SYNC
SENSE
V
IN
INTV
CC
GATE
GND
LTC1871-7
+
R4
J1
10
9
8
7
6
1
2
3
4
5
C
VCC
PSEUDO-KELVIN
GROUND CONNECTION
C
IN
M1
D1
L1
V
IN
GND
18717 F19
V
OUT
SWITCH
NODE
C
OUT
R
C
R
S
R1
R
T
BOLD LINES INDICATE HIGH CURRENT PATHS
R2
C
C
R3
+