Datasheet

LTC1863L/LTC1867L
8
1863l7lfc
TEST CIRCUITS
TIMING DIAGRAMS
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
V
DD
GND
SDI
SDO
SCK
CS/CONV
V
REF
REFCOMP
LTC1863L/
LTC1867L
–
+
+
DIGITAL
I/O
2.7V TO 3.6V
10μF
2.5V
10μF
2.2μF
1.25V
±1.25V
DIFFERENTIAL
INPUTS
2.5V
SINGLE-ENDED
INPUT
1863L7L TCD
TYPICAL CONNECTION DIAGRAM
Load Circuits for Access Timing Load Circuits for Output Float Delay
3k
(A) Hi-Z TO V
OH
AND V
OL
TO V
OH
C
L
3k
2.7V
SDOSDO
(B) Hi-Z TO V
OL
AND V
OH
TO V
OL
C
L
1863L7L TC01
3k
(A) V
OH
TO Hi-Z
C
L
3k
2.7V
SDOSDO
(B) V
OL
TO Hi-Z
C
L
1863L7L TC02
t
1
(For Short Pulse Mode)
t
2
(SDO Valid After SCK↓)
t
3
(SDO Valid Hold Time After SCK↓)
t
4
(SDO Valid After CS/CONV↓)
t
5
(SDI Setup Time Before SCK↑)
t
6
(SDI Hold Time After SCK↑)
t
7
(SLEEP Mode Wake-Up Time) t
8
(BUS Relinquish Time)
1863L7L TD01a
t
1
CS/CONV
50%
50%
t
3
0.45V
1.9V
0.45V
SDO
1863L7L TD01b
t
2
SCK
t
4
CS/CONV
SDO
1.9V
0.45V
0.45V
1863L7L TD01c
Hi-Z
t
6
1.9V
0.45V
t
5
SCK
SDI
1.9V
1.9V
0.45V
1863L7L TD01d
50%
50%
t
7
SCK
CS/CONV
1863L7L TD01e
SLEEP BIT (SLP = 0)
READ-IN
t
8
CS/CONV
SDO
1.9V
1863L7L TD01f
10%
90%
Hi-Z