Datasheet
LTC1864/LTC1865
13
18645fb
LTC1864 OPERATION
Operating Sequence
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to t
CONV
, the conversion is
fi nished. If CONV is left high after this time, the LTC1864
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefi nitely. See Figure 1.
Analog Inputs
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN
+
”
and “IN
–
” inputs. A zero code will occur when IN
+
minus
IN
–
equals zero. Full scale occurs when IN
+
minus IN
–
equals V
REF
minus 1LSB. See Figure 2. Both the “IN
+
” and
“IN
–
” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN
–
”
is grounded and V
REF
is tied to V
CC
, a rail-to-rail input
span will result on “IN
+
” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1864 defi nes
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from V
CC
to 1V.
APPLICATIONS INFORMATION
Figure 1. LTC1864 Operating Sequence
Figure 2. LTC1864 Transfer Curve Figure 3. LTC1864 with Rail-to-Rail Input Span
CONV
t
CONV
SCK
SDO
16151413121110987654321
B15
B14 B12 B10 B8 B6 B4 B2 B0*
Hi-Z
18645 F01
Hi-Z
B13
B11 B9 B7 B5 B3 B1
SLEEP MODE
t
SMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
t
suCONV
0V
1LSB
V
REF
– 2LSB
V
REF
– 1LSB
V
REF
V
IN
*
*V
IN
= IN
+
– IN
–
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
18645 F02
1
2
3
4
8
7
6
5
V
REF
IN
+
IN
–
GND
V
CC
SCK
SDO
CONV
LTC1864
18645 F03
V
IN
= 0V TO V
CC
V
CC
1μF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS