Datasheet

8
LTC1864L/LTC1865L
sn18645L 18645Lfs
Load Circuit for t
dDO
, t
r
, t
f
, t
dis
and t
en
Voltage Waveforms for SDO Rise and Fall Times, t
r
, t
f
Voltage Waveforms for SDO Delay Times, t
dDO
and t
hDO
Voltage Waveforms for t
en
SDO
3k
20pF
TEST POINT
V
CC
t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
1864 TC01
SCK
SDO
V
IL
t
dDO
t
hDO
V
OH
V
OL
1864 TC02
1864 TC03
CONV
SDO
t
en
SDO
t
r
t
f
1864 TC04
V
OH
V
OL
TEST CIRCUITS
Voltage Waveforms for t
dis
SDO
WAVEFORM 1
(SEE NOTE 1)
V
IH
t
dis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONV
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1864 TC05
FUNCTIONAL BLOCK DIAGRA
UU
W
1864/65 BD
16-BIT
SAMPLING
ADC
BIAS AND
SHUTDOWN
CONVERT
CLK
SERIAL
PORT
16 BITS
IN
+
(CH0)
IN
–
(CH1)
V
CC
V
REF
SDO
GND
CONV
(SDI) SCK
PIN NAMES IN
PARENTHESES
REFER TO LTC1865L
DATA OUT
DATA IN
+
–