Datasheet

12
LTC1864L/LTC1865L
sn18645L 18645Lfs
APPLICATIO S I FOR ATIO
WUUU
LTC1864L Evaluation Circuit Schematic
U12B
74AC109
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
JP8
246
135
JP9
246
135
2
3
4
1
5
6
7
8
10
9
8
3.3V
DIG
3.3V
DIG
3.3V
DIG
3.3V
DIG
3.3V
DIG
15V
–15V
3.3V
DIG
3.3V
DIG
3.3V
AN
3.3V
DIG
3.3V
DIG
3.3V
DIG
C16
0.1µF
C23
0.1µF
C5
0.1µF
C6
0.1µF
C24
0.1µF
C18
0.1µF
C17
0.1µF
3.3V
DIG
3.3V
DIG
3.3V
DIG
C13
0.1µF
C12
10µF
6.3V
1206
C14
0.1µF
U12A
74AC109
U10
LTC1799
RESET
CLK
P0
P1
P2
P3
ENP
GND
V
CC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U6
74HC163AD
J
K
CLK
CLR
PRE
Q
Q
GND
V
CC
1
2
3
5
4
V
+
GND
SET
DIV
14
13
12
15
11
J
K
CLK
CLR
PRE
Q
Q
GND
V
CC
16
16
U9B
74AC00
U9A
74AC00
U13B
74AC32
RESET
CLK
P0
P1
P2
P3
ENP
GND
V
CC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U7
74HC163AD
R10
10k
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
J4
3201S40G1
QB
QC
QD
QE
QF
QG
QH
GND
V
CC
QA
A
OENB
LCLK
SCLK
RESET
SQH
RN1
330
QB
QC
QD
QE
QF
QG
QH
GND
V
CC
QA
A
OENB
LCLK
SCLK
RESET
SQH
R9
51Ω
C8
470pF
1205
C9
100pF
1206
C7
100pF
1206
C20
0.1µF
C1
0.1µF
C4
0.1µF
C21
47pF
C22
47pF
C10
0.1µF
3.3V
DIG
C15
0.1µF
3.3V
DIG
C19
0.1µF
C2
1µF
10V
0805
C3
10µF
6.3V
1206
–IN
JP3
BUF
JP2
JP1
+IN
R1
100Ω
1206
R3
2Ω
R2
100Ω
V
IN
V
OUT
GND
U1
LT1460DCS8-2.5
V
IN
V
OUT
GND
R4
2Ω
15V
15V
IN
+
IN
+
AGND
IN
–
IN
–
V
REF
+IN
–IN
GND
V
CC
SCLK
D
OUT
CONV
U8A
74AC14
U8B
74AC14
U8E
74AC14
U8D
74AC14
U8F
74AC14
OUT
15V
3.3V
AN
U4
74HC595ADT
U5
74HC595ADT
U9C
74AC00
U9D
74AC00
U13A
74AC32
U13D
74AC32
U13C
74AC32
ANALOG GROUND PLANE
CLK
JP6
CLK
JP7
EXTCK
JP4
CONV
J1
J2
E1
E8
E9
U2
OPT
U3
LTC1864LAIMS8
1
2
3
4
8
7
6
5
R6
402Ω
1%
R5
402Ω
1%
1
2
3
4
8
7
6
5
2
3
3
3
3
1
2
2
1
6
7
2
1
2
3
3
3
2
1
2
1
4
4
6
1
2
3
CONV
DGND
DGND
DOUT
CLKOUT
CLKIN
ENABLE
DATA
U8C
74AC14
E2
E3
E7
E6
E4
E5
J3
NOTES: UNLESS OTHERWISE SPECIFIED
INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2;
ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5.
1864/65 AI1
R7
20k
LT1121-3.3
CKIN
CKIN
EXT
INT
EXT
INT
R8
1M
P0
P0
P1
P1
P2
P2
P3
P3
1
IN
+
IN
–
BUF
ON
OFF
GND
EN
JP5
3
2
1
GND
EXT
5632
5632
5632