Datasheet

22
LTC1854/LTC1855/LTC1856
185456fa
APPLICATIO S I FOR ATIO
WUUU
18545 F13
ADC
+
LTC1854/LTC1855/LTC1856
DIGITAL
SYSTEM
OV
DD
DGND
24 21
ADC
–
10μF
DV
DD
20
10μF
AV
DD
19
AGND
14, 17, 18
10μF
REFCOMP
16
10μF
V
REF
15
12
MUXOUT
+
LTC1854/
LTC1855/
LTC1856
MUXOUT
–
10
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
11
13
1μF
ANALOG GROUND PLANE
DIGITAL
GROUND PLANE
+
–
Figure 13. Power Supply Grounding Practice
LTC1855/LTC1856 can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply pins, the reference and reference buffer
output is very important. Low impedance common returns
for these bypass capacitors are essential to low noise op-
eration of the ADC, and the foil width for these tracks should
be as wide as possible. Also, since any potential difference
in grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the ADC through a wide, low inductance path.