Datasheet

11
LTC1854/LTC1855/LTC1856
185456fa
t
2
(CONVST to BUSY Delay)
t
2
CONVST
BUSY
2.4V
0.4V
18545 TD02
t
6
(Delay Time, SCK to SDO Valid)
t
7
(Time from Previous Data Remains Valid After SCK)
t
6
t
7
SCK
SDO
2.4V
0.4V
0.4V
18545 TD04
t
8
(SDO Valid After RD)
t
8
RD
SDO
2.4V
0.4V
0.4V
18545 TD05
Hi-Z
t
9
(RD to SCK Setup Time)
t
9
0.4V
2.4V
18545 TD06
RD
SCK
TI I G DIAGRA S
WUW
t
1
(For Short Pulse Mode)
t
1
CONVST
50%
18545 TD01
50%
t
3
, t
4
, t
5
(SCK Timing)
SCK
18545 TD03
t
4
t
5
t
3
Load Circuits for Access Timing
1k
(A) Hi-Z TO V
OH
AND V
OL
TO V
OH
25pF
1k
5V
DNDN
(B) Hi-Z TO V
OL
AND V
OH
TO V
OL
25pF
18545 TC01
Load Circuits for Output Float Delay
1k
(A) V
OH
TO Hi-Z
25pF
1k
5V
DNDN
(B) V
OL
TO Hi-Z
25pF
18545 TC02
TEST CIRCUITS