Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SSOP 28

LTC1854/LTC1855/LTC1856

185456fa

COM

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

MUXOUT

–

ADC

–

AGND1

CONVST

SCK

SDI

DGND

SDO

BUSY

AGND3

AGND2

REFCOMP

REF

LTC1854/

LTC1855/

LTC1856

SOFTWARE-PROGRAMMABLE

SINGLE-ENDED OR

DIFFERENTIAL INPUTS

±10V BIPOLAR INPUT RANGE

10μF

0.1μF 10μF

10μF 0.1μF1μF

10μF

3V TO 5V

2.5V

0.1μF

μP

CONTROL

LINES

0.1μF

8-Channel, ±10V Input

12-/14-/16-Bit, 100ksps ADC

Converters with Shutdown

The LTC

1854/LTC1855/LTC1856 are 8-channel, low

power, 12-/14-/16-bit, 100ksps, analog-to-digital con-

verters (ADCs). These ADCs operate from a single 5V

supply and the 8-channel multiplexer can be programmed

for single-ended inputs, pairs of differential inputs, or

combinations of both. In addition, all channels are fault

protected to ±30V. A fault condition on any channel will

not affect the conversion result of the selected channel.

An onboard precision reference minimizes external com-

ponents. Power dissipation is 40mW at 100ksps and lower

in two power shutdown modes (27.5mW in Nap mode and

40mW in Sleep mode.) DC specifications include ±3LSB

INL for the LTC1856, ±1.5LSB INL for the LTC1855 and

±1LSB for the LTC1854.

The internal clock is trimmed for 5ms maximum conver-

sion time and the sampling rate is guaranteed at 100ksps.

A separate convert start input and data ready signal (BUSY)

ease connections to FIFOs, DSPs and microprocessors.

■

Single 5V Supply

■

Sample Rate: 100ksps

■

8-Channel Multiplexer with ±30V Protection

■

±10V Bipolar Input Range

Single Ended or Differential

■

±3LSB INL for the LTC1856, ±1.5LSB INL for the

LTC1855, ±1LSB INL for the LTC1854

■

Power Dissipation: 40mW (Typ)

■

SPI/MICROWIRE

Compatible Serial I/O

■

Power Shutdown: Nap and Sleep

■

SINAD: 87dB (LTC1856)

■

Operates with Internal or External Reference

■

Internal Synchronized Clock

■

28-Pin SSOP Package

100kHz, 12-Bit/14-/16-Bit Sampling ADC

■

Industrial Process Control

■

Multiplexed Data Acquisition Systems

■

High Speed Data Acquisition for PCs

■

Digital Signal Processing

LTC1856 Typical INL Curve

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

CODE

–32768

INL (LSB)

0.5

1.0

32767

185456 G01

–0.5

–1.0

–2.0

–16384

16384

–1.5

2.0

1.5

Summary of content (24 pages)

PAGE 1
LTC1854/LTC1855/LTC1856 8-Channel, ±10V Input 12-/14-/16-Bit, 100ksps ADC Converters with Shutdown DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1854/LTC1855/LTC1856 are 8-channel, low power, 12-/14-/16-bit, 100ksps, analog-to-digital converters (ADCs). These ADCs operate from a single 5V supply and the 8-channel multiplexer can be programmed for single-ended inputs, pairs of differential inputs, or combinations of both. In addition, all channels are fault protected to ±30V.
PAGE 2
LTC1854/LTC1855/LTC1856 W W W AXI U U ABSOLUTE U U W PACKAGE/ORDER I FOR ATIO RATI GS (Notes 1, 2) Supply Voltage (OVDD = DVDD = AVDD = VDD) ........... 6V Ground Voltage Difference DGND, AGND1, AGND2, AGND3 ...................... ±0.3V Analog Input Voltage ADC+, ADC– (Note 3) ...................(AGND1 – 0.3V) to (AVDD + 0.3V) CH0-CH7, COM .................................................. ±30V Digital Input Voltage (Note 4) ...... (DGND – 0.3V) to 10V Digital Output Voltage .... (DGND – 0.
PAGE 3
LTC1854/LTC1855/LTC1856 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25∞C. (Note 5) PARAMETER CONDITIONS Analog Input Range CH0 to CH7, COM MIN Capacitance Input Leakage Current MAX UNITS ±10 V ADC – ±2.
PAGE 4
LTC1854/LTC1855/LTC1856 U U U I TER AL REFERE CE CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25∞C. (Note 5) PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 VREF Output Temperature Coefficient IOUT = 0 VREF Output Impedance –0.1mA £ IOUT £ 0.1mA VREFCOMP Output Voltage IOUT = 0 ● MIN TYP MAX UNITS 2.475 2.50 2.525 V ±10 ppm/∞C 8 kW 4.
PAGE 5
LTC1854/LTC1855/LTC1856 WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25∞C.
PAGE 6
LTC1854/LTC1855/LTC1856 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC1856 Typical INL Curve 2.0 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –32768 –16384 0 16384 0 MAGNITUDE (dB) 1.5 DNL (LSB) INL (LSB) 2.0 –2.0 –32768 32767 –16384 CODE 0 16384 0 LTC1855 Nonaveraged 4096-Point FFT Plot 0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) 0 –0.2 0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –4096 0 4096 MAGNITUDE (dB) 1 0.
PAGE 7
LTC1854/LTC1855/LTC1856 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC1856 SINAD vs Input Frequency 90 84 82 80 78 CHANNEL-TO-CHANNEL OFFSET ERROR MATCHING (LSBs) TOTAL HARMONIC DISTORTION (dB) 86 SINAD (dB) 1.0 –70 88 –80 –90 –100 76 74 1 10 INPUT FREQUENCY (kHz) 1 10 INPUT FREQUENCY (kHz) 75 70 65 –80 –90 –100 1 10 INPUT FREQUENCY (kHz) LTC1854 SINAD vs Input Frequency –0.25 –0.5 –50 100 100 185456 G16 75 100 0.25 0.20 –70 –80 –90 –100 0.15 0.10 0.05 0 –0.05 –0.10 –0.
PAGE 8
LTC1854/LTC1855/LTC1856 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC1856 Channel-to-Channel Gain Error Matching vs Temperature LTC1855 Channel-to-Channel Gain Error Matching vs Temperature 1.0 LTC1854 Channel-to-Channel Gain Error Matching vs Temperature 0.25 0.5 0.5 0 –0.5 CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSB) CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSBs) CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSBs) 0.20 0.25 0 –0.25 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –1.
PAGE 9
LTC1854/LTC1855/LTC1856 U U U PI FU CTIO S COM (Pin 1): Common Input. This is the negative reference point for all single-ended inputs. It must be free of noise and is usually connected to the analog ground plane. CH0 (Pin 2): Analog MUX Input. AGND1 (Pin 14): Analog Ground. VREF (Pin 15): 2.5V Reference Output. Bypass to analog ground with a 1mF tantalum capacitor. CH2 (Pin 4): Analog MUX Input. REFCOMP (Pin 16): Reference Buffer Output. Bypass to analog ground with a 10mF tantalum and a 0.
PAGE 10
LTC1854/LTC1855/LTC1856 U U U PI FU CTIO S DGND (Pin 24): Digital Ground. RD (Pin 27): Read Input. This active low signal enables the digital output pin SDO and enables the serial interface, SDI and SCK are ignored when RD is high. SDI (Pin 25): Serial Data Input. SCK (Pin 26): Serial Data Clock. CONVST (Pin 28): Conversion Start. The ADC starts a conversion on CONVST’s rising edge.
PAGE 11
LTC1854/LTC1855/LTC1856 TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay 5V 5V 1k DN 1k DN 1k DN (B) Hi-Z TO VOL AND VOH TO VOL (A) Hi-Z TO VOH AND VOL TO VOH DN 1k 25pF 25pF 25pF 25pF (B) VOL TO Hi-Z (A) VOH TO Hi-Z 18545 TC01 18545 TC02 W UW TI I G DIAGRA S t 2 (CONVST to BUSY Delay) t2 t1 (For Short Pulse Mode) CONVST 2.4V t1 50% 50% CONVST BUSY 0.
PAGE 12
LTC1854/LTC1855/LTC1856 WU W TI I G DIAGRA S t 10 (SDI Setup Time Before SCK ) t11 (SDI Hold Time After SCK ) t11 t10 2.4V SCK SDI 2.4V SCK 2.4V 0.4V 2.4V 0.4V SDI 18545 TD08 18545 TD07 t 12 (SDO Valid Before BUSY , RD = 0) t 13 (BUS Relinquish Time) t13 t12 2.4V BUSY SDO 2.4V RD B15 SDO 2.
PAGE 13
LTC1854/LTC1855/LTC1856 U W U U APPLICATIO S I FOR ATIO OVERVIEW The LTC1854/LTC1855/LTC1856 are innovative, multichannel ADCs. The on-chip resistors provide attenuation and offset for each channel. The precisely trimmed attenuators ensure an accurate input range. Because they precede the multiplexer, errors due to multiplexer on-resistance are eliminated. The input word selects the single ended or differential inputs for each channel or pair of channels.
PAGE 14
LTC1854/LTC1855/LTC1856 U W U U APPLICATIO S I FOR ATIO DVDD AVDD MUX ADDRESS CH0 CONVST CONTROL LOGIC CH1 SDI INTERNAL CLOCK • • • BUSY INPUT MUX SCK + 12-/14-/16-BIT SAMPLING ADC CH7 – COM RD DATA OUT SERIAL I/O OVDD SDO 4.096V 2.5V REFERENCE 8k MUXOUT– MUXOUT+ ADC+ 1.6384X ADC– 18545 F01 VREF AGND1 REFCOMP AGND2 AGND3 DGND Figure 1. LTC1854/LTC1855/LTC1856 Simplified Equivalent Circuit AIN+ CH0 LT1792: Single, low noise JFET input op amp, ±5V supplies.
PAGE 15
LTC1854/LTC1855/LTC1856 U W U U APPLICATIO S I FOR ATIO available at VREF (Pin 15). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at REFCOMP (Pin 16). The REFCOMP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade. 15 VREF 2.5V 8k 1μF 2.
PAGE 16
LTC1854/LTC1855/LTC1856 U W U U APPLICATIO S I FOR ATIO DC PERFORMANCE One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the MUX and the resulting output codes are collected over a large number of conversions. For example in Figure 5 the distribution of output code is shown for a DC input that has been digitized 4096 times.
PAGE 17
Hi-Z DON’T CARE Hi-Z DON’T CARE SGL/ DIFF SGL/ DIFF t4 1 t4 1 B15 (MSB) t8 t5 t10 t3 SGL/ DIFF t8 t5 t10 t3 t10 B15 (MSB) t9 t12 B15 (MSB) t9 DON’T CARE t5 B14 SELECT 0 4 5 X B12 B11 B9 t7 t6 NAP 7 B8 SLEEP 8 tACQ B1 DON’T CARE 15 B0 16 t2 t1 tCONV t12 B15 (MSB) SGL/ DIFF 1 B14 ODD/ SIGN 2 SELECT 0 4 X 5 X 6 NAP 7 SLEEP SELECT 1 3 SELECT 0 4 B13 B12 B11 X 5 B10 X 6 B9 t7 t6 NAP 7 B8 SLEEP 8 tACQ B1 DON’T CARE 15 B0 16 t2
PAGE 18
LTC1854/LTC1855/LTC1856 U W U U APPLICATIO S I FOR ATIO SERIAL DATA INPUT (SDI) INTERFACE The LTC1854/LTC1855/LTC1856 communicate with microprocessors and other external circuitry via a synchronous, full duplex, 3-wire serial interface (see Figure 7). The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex).
PAGE 19
LTC1854/LTC1855/LTC1856 U W U U APPLICATIO S I FOR ATIO MUX ADDRESS The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the + and – signs in the selected row of Table 1. Note that in differential mode (SGL/DIFF = 0) measurements are limited to four adjacent input pairs with either polarity.
PAGE 20
DON’T CARE Hi-Z tCONV DON’T CARE tCONV DON’T CARE B15 (MSB) SGL/ DIFF 3 B13 B15 (MSB) SGL/ DIFF 1 SGL/ DIFF 1 SELECT 0 4 X 5 X 6 B14 ODD/ SIGN 2 B14 ODD/ SIGN 2 B12 SELECT 0 4 B10 X 5 B9 NAP = 1 7 X 6 B8 SLEEP = 0 8 B11 B10 B9 A/D RESULT FROM PREVIOUS CONVERSION B12 NAP 7 SELECT 0 4 X 5 X 6 B13 B11 SLEEP A/D RESULT NOT VALID B12 B10 tCONV Hi-Z NAP B15 MSB SGL/ DIFF 1 SELECT 1 B8 SLEEP = 1 8 B14 B0 16 B13 B9 NAP 7 B8 SLEEP = 0 8 B1
PAGE 21
LTC1854/LTC1855/LTC1856 U W U U APPLICATIO S I FOR ATIO SIGNAL-TO-NOISE AND DISTORTION RATIO The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 12 shows a typical SINAD of 87dB with a 100kHz sampling rate and a 1kHz input.
PAGE 22
LTC1854/LTC1855/LTC1856 U W U U APPLICATIO S I FOR ATIO LTC1855/LTC1856 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply pins, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible.
PAGE 23
LTC1854/LTC1855/LTC1856 U PACKAGE DESCRIPTIO G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 9.90 – 10.50* (.390 – .413) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1.25 ±0.12 7.8 – 8.2 5.3 – 5.7 0.42 ±0.03 7.40 – 8.20 (.291 – .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RECOMMENDED SOLDER PAD LAYOUT 2.0 (.079) MAX 5.00 – 5.60** (.197 – .221) 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2.
PAGE 24
LTC1854/LTC1855/LTC1856 U TYPICAL APPLICATIO 5V 5V 10μF 0.1μF 10μF 19 DVDD AVDD 1 COM CONVST 28 MUX ADDRESS 2 CH0 SINGLE-ENDED OR DIFFERENTIAL CHANNEL SELECTION (SEE TABLE 1) INPUT RANGE: ±10V 0.1μF 20 SDI 25 CONTROL LOGIC 3 CH1 BUSY 22 INTERNAL CLOCK • • • INPUT MUX 8-BIT SERIAL DATA INPUT SCK 26 16 SHIFT CLOCK CYCLES + 9 CH7 12-/14-/16-BIT SAMPLING ADC RD 27 DATA OUT OVDD 21 – 10μF SERIAL I/O 4.096V SDO 23 2.5V REFERENCE 16-BIT SERIAL DATA OUT 1.