Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 48

LTC1850/LTC1851

18501f

8-Channel, 10-Bit/12-Bit,

1.25Msps Sampling ADCs

The 10-bit LTC

1850 and 12-bit LTC1851 are complete

8-channel data acquisition systems. They include a flex-

ible 8-channel multiplexer, a 1.25Msps successive approxi-

mation analog-to-digital converter with sample-and-hold,

an internal 2.5V reference and reference buffer amplifier,

and a parallel output interface. The multiplexer can be con-

figured for single-ended or differential inputs, two gain

ranges and unipolar or bipolar operation.

The ADCs have a scan mode that will repeatedly cycle

through all 8 multiplexer channels and can also be

programmed with a sequence of up to 16 addresses and

configurations that can be scanned in succession. The

sequence memory can also be read back. The reference

and buffer amplifier provide pin strappable ranges of

4.096V, 2.5V and 2.048V. The parallel output includes

the 10-bit or 12-bit conversion result plus the 4-bit

multiplexer address. The digital outputs are powered

from a separate supply allowing for easy interface to 3V

digital logic. Typical power consumption is 40mW at

1.25Msps from a single 5V supply.

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Flexible 8-Channel Multiplexer

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Single-Ended or Differential Inputs

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Two Gain Ranges Plus Unipolar and Bipolar

Operation

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1.25Msps Sampling Rate

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Single 5V Supply and 40mW Power Dissipation

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Scan Mode and Programmable Sequencer

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Pin Compatible 10-Bit LTC1850 and 12-Bit LTC1851

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True Differential Inputs Reject Common Mode Noise

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Internal 2.5V Reference

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Parallel Output Includes MUX Address

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Easy Interface to 3V Logic

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Nap and Sleep Shutdown Modes

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High Speed Data Acquisition

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Test and Measurement

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Imaging Systems

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Telecommunications

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Industrial Process Control

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Spectrum Analysis

FEATURES

DESCRIPTIO

APPLICATIO S

BLOCK DIAGRA

BUSY

DIFF

OUT

/S6

OUT

/S5

OUT

/S4

OUT

/S3

D11/S2

D10/S1

D9/S0

SHDN

CONVST

DIFF

UNI/BIP

PGA

OUTPUT

DRIVERS

DATA

LATCHES

OGND

1851 BD

REF AMP

REFCOMP

REFIN

REFOUT

COM

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

8-CHANNEL

MULTIPLEXER

2.5V

REFERENCE

INTERNAL

CLOCK

LTC1851

CONTROL LOGIC

AND

PROGRAMMABLE

SEQUENCER

12-BIT

1.25Msps ADC

, LTC and LT are registered trademarks of Linear Technology Corporation.

CODE

–1.00

INL COC ERROR (LSBs)

–0.50

0.00

0.50

1.00

512 1024 1536 2048

LTC1850/51 G01

2560 3072 3584 4096

Integral Linearity, LTC1851

Summary of content (28 pages)

PAGE 1
LTC1850/LTC1851 8-Channel, 10-Bit/12-Bit, 1.25Msps Sampling ADCs DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The 10-bit LTC®1850 and 12-bit LTC1851 are complete 8-channel data acquisition systems. They include a flexible 8-channel multiplexer, a 1.25Msps successive approximation analog-to-digital converter with sample-and-hold, an internal 2.5V reference and reference buffer amplifier, and a parallel output interface.
PAGE 2
LTC1850/LTC1851 W W W AXI U U ABSOLUTE RATI GS OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 6V Analog Input Voltage (Note 3) ..... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ....................– 0.3V to 10V Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 500mW Ambient Operating Temperature Range LTC1850C/LTC1851C ............................
PAGE 3
LTC1850/LTC1851 U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 6) PARAMETER CONDITIONS MIN Resolution (No Missing Codes) Integral Linearity Error ● (Note 7) Differential Linearity Error Offset Error (Bipolar and Unipolar) Gain = 1 (PGA = 1) Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) (Note 8) REFCOMP ≥ 2V REFCOMP ≥ 2V LTC1850 LTC1851 TYP MAX MIN TYP MAX 10 12 ±0.25 ± 0.5 ±0.
PAGE 4
LTC1850/LTC1851 W U DY A IC ACCURACY (Note 5) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio Unipolar, PGA = 0 Unipolar, PGA = 1 Bipolar, PGA = 0 Bipolar, PGA = 1 47kHz Input Signal Signal-to-(Noise + Distortion) Ratio Unipolar, PGA = 0 Unipolar, PGA = 1 Bipolar, PGA = 0 Bipolar, PGA = 1 47kHz Input Signal Total Harmonic Distortion Unipolar, PGA = 0 Unipolar, PGA = 1 Bipolar, PGA = 0 Bipolar, PGA = 1 47kHz Input Signal, First 5 Harmonics Spurious-Free Dynamic Range Unipolar, PGA = 0 Unip
PAGE 5
LTC1850/LTC1851 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MAX UNITS VDD Positive Supply Voltage (Note 10) ● 4.75 MIN TYP 5.25 V OVDD Output Positive Supply Voltage (Note 10) ● 2.7 5.25 V IDD Positive Supply Current VDD = VDD = OVDD = 5V, fSAMPLE = 1.
PAGE 6
LTC1850/LTC1851 WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 7
LTC1850/LTC1851 U W TYPICAL PERFOR A CE CHARACTERISTICS Typical DNL, PGA =1, LTC1851 1.00 0.50 0.50 0.50 0.00 –0.50 DNL EOC ERROR (LSBs) 1.00 0.00 –0.50 –1.00 –1.00 0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 512 1024 1536 2048 2560 3072 3584 4096 CODE 0.00 –0.50 –1.
PAGE 8
LTC1850/LTC1851 U W TYPICAL PERFOR A CE CHARACTERISTICS –50 –55 –55 –55 –60 –60 –60 –65 –65 –65 THD –70 –75 –80 –85 3RD HARMONIC –70 THD –75 3RD HARMONIC –80 –85 –90 2ND HARMONIC –95 DISTORTION (dB) –50 DISTORTION (dB) DISTORTION (dB) –50 –90 1000 100 FREQUENCY (kHz) 2ND HARMONIC –80 3RD HARMONIC –85 –100 10 10000 –75 –95 –100 10 THD –70 –90 2ND HARMONIC –95 –100 1000 100 FREQUENCY (kHz) 10000 10 185051 G19 80 80 –55 70 70 60 60 50 50 –60 CMRR (dB) –70
PAGE 9
LTC1850/LTC1851 U W TYPICAL PERFOR A CE CHARACTERISTICS Channel-to-Channel Isolation (Worst Pair), Unipolar Mode, PGA = 0 110 110 100 100 90 ISOLATION (dB) ISOLATION (dB) Channel-to-Channel Isolation (Worst Pair) Bipolar Mode, PGA = 0 LIMIT OF MEASUREMENT 80 70 60 90 LIMIT OF MEASUREMENT 80 70 60 50 0 2M 4M 6M 8M INPUT FREQUENCY (Hz) 50 10M 0 2M 4M 6M 8M INPUT FREQUENCY (Hz) LTC1850/51 G12 LTC1850/51 G15 Channel-to-Channel Isolation (Worst Pair), Bipolar Mode, PGA =1 Channel-to-Channe
PAGE 10
LTC1850/LTC1851 U U U PI FU CTIO S CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can be used single ended relative to the analog input common pin (COM) or differentially in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7). COM (Pin 9): Analog Input Common Pin. For single-ended operation (DIFF = 0), COM is the “–” analog input. COM is disabled when DIFF is high. REFOUT (Pin 10): Internal 2.5V Reference Output. Requires bypass to analog ground plane with 1µF.
PAGE 11
LTC1850/LTC1851 U U U PI FU CTIO S D9/S0 (Pin 23, LTC1851): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. D6 to D0 (Pins 24 to 30, LTC1850): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND.
PAGE 12
LTC1850/LTC1851 U U U PI FU CTIO S PIN NAME DESCRIPTION MIN NOMINAL (V) TYP MAX ABSOLUTE MAXIMUM (V) MIN MAX 1 to 8 CH0 to CH7 Analog Inputs 0 VDD – 0.3 VDD + 0.3 9 COM Analog Input Common Pin 0 VDD – 0.3 VDD + 0.3 10 REFOUT 2.5V Reference Output – 0.3 VDD + 0.3 11 REFIN Reference Buffer Input 12 REFCOMP Reference Buffer Output 13 GND Ground, Substrate Ground 14 VDD Supply 4.75 5 15 VDD Supply 4.
PAGE 13
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO The LTC1850/LTC1851 are complete and very flexible data acquisition systems. They consist of a 10-bit/12-bit, 1.25Msps capacitive successive approximation A/D converter with a wideband sample-and-hold, a configurable 8-channel analog input multiplexer, an internal reference and reference buffer amplifier, a 16-bit parallel digital output and digital control logic including a programmable sequencer.
PAGE 14
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa ± fb).
PAGE 15
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO Table 2. Input Span Table INPUT SPAN UNI/BIP PGA 0 0 0 – REFCOMP/2 REFCOMP = 4.096V 0 – 2.048V 0 1 0 – REFCOMP 0 – 4.096V 1 0 ±REFCOMP/4 ±1.024V 1 1 ±REFCOMP/2 ±2.048V It should be noted that the bipolar input span of the LTC1850/LTC1851 does not allow negative inputs with respect to ground. The LTC1850/LTC1851 have a unique differential sample-and-hold circuit that allows rail-to-rail inputs.
PAGE 16
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO LT1468/LT1469: Single and Dual 90MHz Voltage Feedback Amplifier. ±5V to ±15V supplies. 7mA supply current per amplifier. Lowest noise and low distortion. LT1630/LT1631: Dual and Quad 30MHz Rail-to-Rail Voltage Feedback Amplifiers. Single 3V to ±15V supplies. 3.5mA supply current per amplifier. Low noise and low distortion. LT1632/LT1633: Dual and Quad 45MHz Rail-to-Rail Voltage Feedback Amplifiers. Single 3V to ±15V supplies. 4.
PAGE 17
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO the offset applied to the “–” input. For single-ended inputs, this offset should be applied to the COM pin. For differential inputs, the “–” input is dictated by the MUX address. For zero offset error, apply 0.
PAGE 18
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog inputs, reference or analog power supply lines. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible.
PAGE 19
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO SUPPLY BYPASSING CS High quality, low series resistance ceramic 10µF bypass capacitors should be used. Surface mount ceramic capacitors provide excellent bypassing in a small board space. Alternatively, 10µF tantalum capacitors in parallel with 0.1µF ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible.
PAGE 20
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 7), CS is tied low.
PAGE 21
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO tCONV CS = LOW t5 t8 CONVST t13 t6 BUSY t9 t12 RD t10 DATA t11 DATA N 1851 F07 Figure 7. Mode 2 CONVST Starts a Conversion. Data is Read by RD tCONV CS = LOW t8 RD = CONVST t11 t6 BUSY t10 DATA t7 DATA (N – 1) DATA N DATA N DATA (N + 1) 1851 F08 Figure 8. Slow Memory Mode Timing tCONV CS = LOW t8 RD = CONVST t6 t11 BUSY t10 DATA DATA (N – 1) DATA N 1851 F09 Figure 9.
PAGE 22
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO In slow memory mode, the processor applies a logic low to RD ( = CONVST), starting the conversion. BUSY goes low, forcing the processor into a Wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the processor, and the processor takes RD ( = CONVST) back high and reads the new conversion data.
PAGE 23
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO S6 DIFF S5 A2 S4 A1 S3 A0 S2 UNI/BIP S1 PGA S0 EOS • • • • • • • • • • • • • • • • • • • • • LOCATION 0000 LOCATION 0001 LOCATION 0010 LOCATION 1110 LOCATION 1111 1851 F10 Figure 10. Sequencer Memory Block Diagram The sequencer is accessed by taking the M1 mode pin high. With M1 high, the sequencer memory is accessed by taking the M0 mode pin low.
PAGE 24
LTC1850/LTC1851 U W U U APPLICATIO S I FOR ATIO Sequence Run Mode Once the sequencer is programmed, M0 is taken high. BUSY will also come back high enabling CONVST and the next falling CONVST will begin a conversion using the MUX address and input configuration stored in location 0000 of the sequencer memory.
PAGE 25
D6 TO D0 (LTC1850) D8 TO D0 (LTC1851) S6 TO S0 Hi-Z L0CATION 0001 L0CATION 0000 PGA Hi-Z L0CATION 0001 L0CATION 0000 UNI/BIP BUSY L0CATION 0001 L0CATION 0000 A2 TO A0 t19 L0CATION 0001 t16 L0CATION 0000 t20 t17 DIFF RD WR CONVST t23 LOCATION 0000 t11 t24 Figure 11.
PAGE 26
Hi-Z DIFFOUT A2OUT TO A0OUT D9 TO D0 (LTC1850) D11 TO D0 (LTC1851) L0CATION 0010 L0CATION 0010 L0CATION 0010 L0CATION 0010 t23 t25 t6 t8 DATA 0000 CONVERT 0001 Figure 12.
PAGE 27
LTC1850/LTC1851 U PACKAGE DESCRIPTIO FW Package 48-Lead Plastic TSSOP (6.1mm) (Reference LTC DWG # 05-08-1651) 12.4 – 12.6* (.488 – .496) 0.95 ±0.10 8.1 ±0.10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 6.2 ±0.10 7.9 – 8.3 (.311 – .327) 0.32 ±0.05 0.50 TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RECOMMENDED SOLDER PAD LAYOUT 1.20 (.0473) MAX 6.0 – 6.2** (.236 – .244) 0° – 8° -T.10 C -C0.09 – 0.20 (.0035 – .008) 0.45 – 0.75 (.018 – .029) 0.
PAGE 28
LTC1850/LTC1851 U TYPICAL APPLICATIO Data buffering using two IDT7202LA15 1k x 9-bit FIFOs allows rapid collection of 1024 samples and simple interface to low power, low speed, 8-bit microcontrollers. Data and channel information are clocked in simultaneously and read out as two bytes using READ HIGH FIFO and READ LOW FIFO lines. In the event of bus contention, resistors limit peak output current.