Datasheet

10
LTC1779
Foldback Current Limiting
As described in the Output Diode Selection, the worst-
case dissipation occurs with a short-circuited output
when the diode conducts the current limit value almost
continuously. To prevent excessive heating in the diode,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding di-
odes D
FB1
and D
FB2
between the output and the I
TH
/RUN
pin as shown in Figure 6. In a hard short (V
OUT
= 0V), the
current will be reduced to approximately 50% of the
maximum output current.
Figure 7. LTC1779 Layout Diagram (See PC Board Layout Checklist)
APPLICATIO S I FOR ATIO
WUUU
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1779. These items are illustrated graphically in the
layout diagram in Figure 7. Check the following in your
layout:
1. Large switch currents flow into the input capacitor C
IN
,
the power switch and the Schottky diode D1. The loop
formed by these components should be as small as
possible.
2. Is the input decoupling capacitor (0.1µF) connected
closely between V
IN
(Pin 5) and ground (Pin 2)?
3. Keep the switching node SW away from sensitive small
signal nodes.
4. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of C
OUT
and signal
ground. Locate R1 and R2 close to the V
FB
pin.
L1
SW
R1
BOLD LINES INDICATE HIGH CURRENT PATHS
R2
D1
R
S
V
IN
V
OUT
1779 F07
0.1µF
C
OUT
C
ITH
R
ITH
+
C
IN
+
I
TH
/RUN
LTC1779
GND
V
FB
6
5
4
1
2
3
SW
V
IN
SENSE
–
Figure 6. Foldback Current Limiting
V
FB
I
TH
/RUN
V
OUT
LTC1779
R1
1779 F06
R2
D
FB1
D
FB2
+