Datasheet

8
LTC1771
Power MOSFET Selection
An external P-channel power MOSFET must be selected
for use with the LTC1771. The main selection criteria for
the power MOSFET are the threshold voltage V
GS(TH)
and
the “on” resistance R
DS(ON)
, reverse transfer capacitance
and total gate charge.
Since the LTC1771 can operate down to input voltages as
low as 2.8V, a sublogic level threshold MOSFET (R
DS(ON)
guaranteed at V
GS
= 2.5V) is required for applications that
work close to this voltage. When these MOSFETs are used,
make sure that the input supply to the LTC1771 is less than
the absolute maximum V
GS
rating (typically 12V), as the
MOSFET gate will see the full supply voltage.
The required R
DS(ON)
of the MOSFET is governed by its
allowable power dissipation. For applications that may
operate the LTC1771 in dropout, i.e. 100% duty cycle, at
its worst case the required R
DS(ON)
is given by:
R
P
I
DS ON
P
OUT MAX P
()
()
=
()
+
()
2
1 δ
where P
P
is the allowable power dissipation and δ
P
is the
temperature dependency of R
DS(ON)
. (1 + δ
P
) is generally
given for a MOSFET in the form of a normalized R
DS(ON)
vs
temperature curve, but = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
In applications where the maximum duty cycle is less than
100% and the LTC1771 is in continuous mode, the R
DS(ON)
is governed by:
R
P
DC I
DC
VV
VV
DS ON
P
OUT P
OUT D
IN D
()
=
()
+
()
=
+
+
2
1 δ
where DC is the maximum operating duty cycle of the
LTC1771.
Catch Diode Selection
The catch diode carries load current during the off-time.
The average diode current is therefore dependent on the
P-channel switch duty cycle. At high input voltages the
diode conducts most of the time. As V
IN
approaches V
OUT
the diode conducts only a small fraction of the time. The
most stressful condition for the diode is when the output
is short-circuited. Under this condition, the diode must
safely handle I
PEAK
at close to 100% duty cycle.
To maximize both low and high current efficiencies, a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage current is
critical to maximize low current efficiency since the leak-
age can potentially exceed the magnitude of the LTC1771
supply current. Low forward drop is critical for high
current efficiency since loss is proportional to forward
drop. The effect of reverse leakage and forward drop on
no- load supply current and efficiency for various Schottky
diodes is shown in Table 1. As can be seen, these are
conflicting parameters and the user must weigh the
importance of each spec in choosing the best diode for the
application.
Table 1. Effect of Catch Diode on Performance
LEAKAGE NO-LOAD EFFICIENCY
DIODE (V
R
= 3.3V) V
F
@ 1A SUPPLY CURRENT AT 10V/1A
MBR0540 0.25µA 0.50V 10.4µA 86.3%
UPS5817 2.8µA 0.41V 11.8µA 88.2%
MBR0520 3.7µA 0.36V 12.2µA 88.4%
MBRS120T3 4.4µA 0.43V 12.2µA 87.9%
MBRM120LT3 8.3µA 0.32V 14.0µA 89.4%
MBRS320 19.7µA 0.29V 20.0µA 89.8%
C
IN
and C
OUT
Selection
At higher load currents, when the inductor current is
continuous, the source current of the P-channel MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
capacitor current is given by:
C
IVVV
V
IN
MAX OUT IN OUT
IN
required I
RMS
=
−
()
[]
12/
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
APPLICATIO S I FOR ATIO
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