Datasheet

12
LTC1771
2. Is the 0.1µF input decoupling capacitor closely con-
nected between V
IN
(Pin 6) and ground (Pin 4)? This
capacitor carries the high frequency peak currents.
3. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of C
OUT
and signal
ground. Locate the feedback resistors right next to the
LTC1771. The V
FB
line should not be routed close to any
nodes with high slew rates.
4. Is the 1000pF decoupling capacitor for the current
sense resistor connected as close as possible to Pins 6
and 7? Ensure accurate current sensing with Kelvin
connections to the sense resistor.
5. Is the (+) plate of C
IN
closely connected to the sense
resistor ? This capacitor provides the AC current to the
MOSFET.
6. Are the signal and power grounds segregated? The
signal ground consists of the (–) plate of C
OUT
, Pin 4 of
the LTC1771 and the resistive divider. The power ground
consists of the Schottky diode anode and the (–) plate
of C
IN
which should have as short lead lengths as
possible.
7. Keep the switching node (SW) and the gate node
(PGATE) away from sensitive small signal nodes, espe-
cially the voltage sensing feedback pin (V
FB
), and mini-
mize their PC trace area.
Design Example
As a design example, assume V
IN
= 10V (nominal), V
IN
=
15V
(MAX)
, V
OUT
= 3.3V, and I
MAX
= 2A. With this informa-
tion, we can easily calculate all the important components.
R
SENSE
= 100mV/2A = 0.05Ω
To optimize low current efficiency, MODE pin is tied to V
IN
to enable Burst Mode operation, thus the minimum induc-
tance necessary is:
L
MIN
= 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH
15µH is chosen for the application.
∆=
+






=Is
VV
H
A
L
35
33 05
15
089.
..
.µ
µ
For the feedback resistors, choose R1 = 1M to minimize
supply current. R2 can then be calculated to be:
R2 = (V
OUT
/1.23 – 1) • R1 = 1.68M
Assume that the MOSFET dissipation is to be limited to
P
P
= 0.25W.
If T
A
= 70°C and the thermal resistance of the MOSFET is
83°C/W, then the junction temperatures will be 91°C and
δ
P
= 0.33. The required R
DS(ON)
for the MOSFET can now
be calculated:
P
W
VV
VV
A
-Channel R
DS(ON)
=
+
+






()( )
=
025
33 05
10 0 5
2133
0 130
2
.
..
.
.
. Ω
Since the gate of the MOSFET will see the full input voltage,
a MOSFET must be selected whose V
GS(MAX)
> 15V. A
P-channel MOSFET that meets both the V
GS(MAX)
and
R
DS(ON)
requirement is the Si6447DQ.
The most stringent requirement for the Schottky diode
occurs when V
OUT
= 0V (i.e., short circuit) at maximum
V
IN
. In this case the worst-case dissipation rises to:
PI V
V
VV
SC AVG D
IN
IN D
D
=
()
+






()
Figure 5. LTC1771 Layout Diagram
APPLICATIO S I FOR ATIO
WUUU
RUN/SS
I
TH
V
FB
GND
V
OUT
R
ITH
C
ITH
C
FF
0.1µF
Q1
D1
R2
R1
1
2
3
4
8
7
6
5
1771 F05
C
SS
C
IN
MODE
MODE
SENSE
V
IN
PGATE
LTC1771
BOLD LINES INDICATE HIGH CURRENT PATHS
+
C
OUT
L
+