Datasheet

11
LTC1771
limiting should be added to reduce the current in propor-
tion to the severity of the fault.
Foldback current limiting is implemented by adding two
diodes in series between the output and the I
TH
pin as
shown in the Functional Diagram. In a hard short (V
OUT
=
0V) the current will be reduced to approximately 25% of
the maximum output current.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC1771 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the
P-channel MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
tt
VV
VV
t
ON OFF
OUT D
IN OUT
ON MIN
=
+
−






>
()
where t
OFF
= 3.5µs and t
ON(MIN)
is generally about 0.4µs
for the LTC1771.
As the on-time approaches t
ON(MIN)
, the LTC1771 will
remain in Burst Mode operation for an increasingly larger
portion of the load range (see Figure 3) and at or below
t
ON(MIN)
will remain in Burst Mode operation 100% of the
time. The output voltage will continue to be regulated, but
the ripple current and ripple voltage will increase.
Mode Pin
Burst Mode operation is disabled by pulling MODE (Pin 8)
below 0.5V. Disabling Burst Mode operation provides a
low noise output spectrum, useful for reducing both audio
and RF interference. It does this by keeping the frequency
constant (for fixed V
IN
) down to much lower load current
(1% to 2% of I
MAX
) and reducing the amount of output
voltage and current ripple at light loads. When Burst Mode
operation is disabled, efficiency is reduced at light loads
and no load supply current increases to 175µA.
Low Supply Operation
Although the LTC1771 can function down to 2.8V, the
maximum allowable output current is reduced when V
IN
decreases below 3.2V. Figure 4 shows the amount of
change as the supply is reduced below 3.2V, where 100%
of maximum load equals 0.1/R
SENSE
. To ensure adequate
output current at V
IN
< 3.2V, simply lower R
SENSE
by the
same percentage as the current reduction in Figure 4.
APPLICATIO S I FOR ATIO
WUUU
ON-TIME (µs)
0
% OF MAXIMUM LOAD
60
80
100
2.0
1771 F03
40
20
0
0.5
1.0
1.5
2.5
Figure 3. Burst Threshold vs On-Time
INPUT VOLTAGE (V)
2.5
100
120
140
4.0 4.5
1771 F04
80
60
3.0 3.5 5.0
40
20
0
MAXIMUM LOAD (%)
Figure 4. Maximum Load vs Input Voltage
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1771. These items are also illustrated graphically in
the layout diagram of Figure 5. Check the following in your
layout:
1. Is the Schottky diode closely connected to the drain of
the external MOSFET and the input cap ground?