LTC1760 Dual Smart Battery System Manager DESCRIPTION FEATURES n n n n n n n n n n n n n n SMBus Charger/Selector for Two Smart Batteries* Voltage and Current Accuracy within 0.2% of Value Reported by Battery Simplifies Construction of “Smart Battery System Manager” Includes All SMBus Charger V1.
LTC1760 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW DCIN, SCP, SCN, CLP, VPLUS, SW to GND ..................................... –0.3V to 32V SCH1, SCH2 to GND ................................... –0.3V to 28V BOOST to GND ........................................... –0.3V to 37V CSP, CSN, BAT1, BAT2 to GND ................... –0.3V to 28V LOPWR, DCDIV to GND ............................. –0.3V to 10V VCC2, VDDS to GND ....................................... –0.
LTC1760 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted.
LTC1760 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.166 1.162 1.19 1.19 1.215 1.
LTC1760 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted. SYMBOL PARAMETER VCOFF VTOC CONDITIONS MIN TYP MAX CH Gate Off Voltage GCH1 GCH2 ILOAD =10μA VGCH1 – VSCH1 VGCH2 – VSCH2 –0.8 –0.8 –0.4 –0.
LTC1760 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted.
LTC1760 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VIH_MODE MODE Input High Voltage (VIH) MIN TYP MAX UNITS VVCC2 = 4.85V l VVCC2 • 0.7 MODE Input Current (IIH) MODE = VVCC2 • 0.7V, VVCC2 = 4.
LTC1760 TYPICAL PERFORMANCE CHARACTERISTICS Charging Voltage Accuracy 10 –5 –10 –15 –20 5 BATTERY CURRENT (mA) Current()–ChargingCurrent() (mA) 0 –5 –10 –15 –20 –25 4700 7132 11996 14428 9564 ChargingVoltage() (mV) 0 16860 800 Dual Battery Discharge Time vs Sequential Battery Discharge (Li-Ion) 2000 15.5 BAT1 CURRENT 14.5 BAT2 CURRENT 14.0 13.5 0 20 1500 1000 500 10.0 DUAL 100 MINUTES 50 100 150 200 TIME (MINUTES) BAT2 VOLTAGE 8.0 SEQUENTIAL 12.0 11.0 BAT1 VOLTAGE 9.
LTC1760 TYPICAL PERFORMANCE CHARACTERISTICS Load Dump 14 BAT1 OUTPUT 90 12 BAT1 VOLTAGE (V) EFFICIENCY (%) 60 50 40 30 10 8 6 4 0 0.025 0.50 0.10 IOUT (A) 2.5 4.0 0 –4 –2 12.0 11.9 VIN = 20V VDAC = 12.288V IDAC = 4000mA TA = 25°C 11.7 11.6 0 2 4 6 8 TIME (ms) 10 12 14 16 0 1000 2000 3000 CHARGE CURRENT (mA) 1760 G08 1760 G07 PowerPath Switching 1 and 2 4000 1760 G09 SMBus Accelerator Operation 16 CLOAD = 20F 15 ILOAD = 0.8A T = 25°C 14 A LOAD VOLTAGE (V) 12.1 11.
LTC1760 PIN FUNCTIONS GB1O (Pin 8): BAT1 Output Switch Gate Drive. Together with GB1I, this pin drives the gate of the P-channel switch in series with the BAT1 input switch. GB1I (Pin 9): BAT1 Input Switch Gate Drive. Together with GB1O, this pin drives the gate of the P-channel switch connected to the BAT1 input. GB2O (Pin 10): BAT2 Output Switch Gate Drive. Together with GB2I, this pin drives the gate of the P-channel switch in series with the BAT2 input switch.
LTC1760 PIN FUNCTIONS LOPWR (Pin 12): LOPWR Comparator Input from SCN External Resistor Divider to GND. If the voltage at LOPWR pin is lower than the LOPWR comparator threshold, then system power has failed and power is autonomously switched to a higher voltage source, if available. cators. Requires an external pullup to VDDS (normal SMBus operating mode). Connected to internal SMBus accelerator. DCDIV (Pin 16): External DC Source Comparator Input from DCIN External Resistor Divider to GND.
LTC1760 BLOCK DIAGRAM GB1I GB1O 9 GB2I GB2O 8 11 GDCI GDCO 10 7 6 100mV SWDC DRIVER 5 SCP 100Ω – SWB2 DRIVER + SWB1 DRIVER SHORT CIRCUIT 4 SCN 32 ILIMIT LIMIT DECODER CHARGE PUMP DCIN 33 VLIMIT VCC2 10μA ON + – GCH1 46 29 SMBALERT SCH1 45 ON SEQUENCER + – GCH2 47 26 MODE CSN 20 VDDS SCH2 48 BAT1 3 BAT2 2 18 SCL AC_PRESENT 22 SDA SMBus INTERFACE 19 SCL1 CHARGE VPLUS 1 23 SDA1 SCN 17 SCL2 21 SDA2 VCC2 25 VCC 40 VCC REGULATOR 30 TH1A SAFETY SIGNAL DECODER GND 24
LTC1760 TABLE OF CONTENTS (For Operation Section) 1 Overview ............................................................................................................................................................................................. 13 2 The SMBus Interface .......................................................................................................................................................................... 13 2.1 SMBus Interface Overview ...............................
LTC1760 OPERATION (Refer to Block Diagram and Typical Application Figure) 1 Overview The LTC1760 is composed of an SMBus interface with dual port capability, a sequencer for managing system power and the charging and discharging of two batteries, a battery charger controller, charge MUX controller, PowerPath controller, a 10-bit current DAC (IDAC) and 11-bit voltage DAC (VDAC).
LTC1760 OPERATION 2.2 Data Bit Definition of Supported SMBus Functions.
LTC1760 OPERATION IA00 IA01 IA02 IA03 IA04 IA05 IA06 IA07 IA08 IA09 IA10 VA00 VA01 VA02 VA03 VA04 VA05 VA06 VA07 VA08 VA10 VA11 VA12 VA09 IR00 IR01 IR02 IR03 IR04 IR05 IR06 IR08 IR09 IR07 VR01 VR02 VR03 VR04 VR05 VR06 VR07 VR00 RESERVED RESERVED OVER_CHARGED RESERVED Register RESERVED N/A 8-bit: 0×16 FULLY_DISCHARGED Status RESERVED 0×16 RESERVED 7-bit: 0001_010b RESERVED Read RESERVED Master 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
LTC1760 OPERATION 2.3 Description of Supported SMBus Functions The functions are described as follows: • The LTC1760 autonomously changes the configuration of the batteries being charged (Polling only). Function Name() (command code) Purpose: Description: Used by the SMBus Host to determine the present state of the LTC1760 and the attached batteries. It also may be used to determine the state of the battery system after the LTC1760 notifies the SMBus Host of a change via SMBALERT.
LTC1760 OPERATION CHARGE_BAT[4:1] Nibble The read only CHARGE_BAT[4:1]nibble is used by the SMBus Host to determine which, if any, battery is being charged. All writes to this nibble will be ignored. Allowed values are: power configuration. It may also be used by the system to prohibit any battery charging. SMBus Protocol: Read or Write Word. Input/Output: word - Refer to “Section 2.2” for bit mapping 0011b: Both Battery 2 and Battery 1 being charged.
LTC1760 OPERATION CALIBRATE_REQUEST Bit CALIBRATE_BAT[4:1] Nibble The read only CALIBRATE_REQUEST bit is set whenever the LTC1760 has determined that one or both of the connected batteries need a calibration cycle. The read/write CALIBRATE_BAT[4:1]nibble is used by the SMBus Host to select the battery to be calibrated or to determine which individual battery is being calibrated. Allowed values are: Allowed read values are: 1b: The LTC1760 has determined that one or both batteries requires calibration.
LTC1760 OPERATION BATTERY_SYSTEM_REVISION Nibble 2.3.5 BatteryMode() (0×03) The read only BATTERY_SYSTEM_REVISION nibble reports the version of the Smart Battery System Manager specification supported. Description: LTC1760 always returns 1000b for this nibble, indicating Version 1.0 without optional PEC support. 2.3.4 LTC() (0×3C) Description: This function returns the LTC version nibble and allows the user to perform expanded Smart Battery System Manager functions.
LTC1760 OPERATION 2.3.7 Current() (0×0A) Purpose: Description: Allows the LTC1760 to determine the maximum charging voltage. This function is used by the LTC1760 to read the actual current being supplied through the battery terminals. Purpose: Allows the LTC1760 to determine how much current a battery is receiving through its terminals and close the charging current servo loop. SMBus Protocol: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master.
LTC1760 OPERATION TERMINATE_CHARGE_RESERVED Bit 2.3.11 AlertResponse() The read only TERMINATE_CHARGE_RESERVED bit is used by the LTC1760 to determine if charging may continue. Description: Allowed values are: 1b: The LTC1760 will not charge this battery. 0b: The LTC1760 may charge this battery if other conditions permit charging. OVER_TEMP_ALARM Bit The read only OVER_TEMP_ALARM bit is used by the LTC1760 to determine if charging may continue.
LTC1760 OPERATION SMB2* HOST SMB* SMB2* BAT2 SMB* HOST SMB1* LTC1760 SMBus CONTROLLER SMB1* BAT1 LTC1760 SMBus CONTROLLER HOST, LTC1760 AND BAT1 CAN COMMUNICATE. BAT2 ORIGINATED COMMANDS ARE IGNORED. BAT1 LTC1760 AND BAT2 CAN COMMUNICATE. HOST AND BAT1 ORIGINATED COMMANDS ARE STRETCHED IF THE LTC1760 IS COMMUNICATING WITH BAT2. (1a) (1b) SMB2* HOST BAT2 SMB* SMB2* BAT2 SMB* HOST SMB1* LTC1760 SMBus CONTROLLER SMB1* BAT1 HOST, LTC1760 AND BAT2 CAN COMMUNICATE.
SDA2 SCL2 SDA1 SCL1 SDA SCL SMBus DUAL PORT Figure 2. LTC1760 Stretches Host’s Communication With Battery 1 While It Completes a Read Of Battery 2.
SDA2 SCL2 SDA1 SCL1 SDA SCL SMBus DUAL PORT Figure 3. LTC1760 Queries Battery 1 Followed By Battery 2 For Requested Current.
LTC1760 OPERATION 2.6 LTC1760 SMBALERT Operation The SMBALERT pin allows the LTC1760 to signal to the SMBus Host that there has been a change of status. This pin is asserted low whenever there is a change in battery presence, AC presence or after a power on reset event. This pin is cleared during an Alert Response or any of the following reads: BatterySystemState(),BatterySystemStateCont(), BatterySystemInfo(), or LTC(). 3 Charging Algorithm Overview 3.
LTC1760 OPERATION 6. The SMBus Host asserts BatterySystemStateCont(CHARGING_INHIBIT) high. 5. The battery responds to an LTC1760 Master read of Alarm() with all charge alarms deasserted. 7. Hardware controlled charging inhibit is asserted (MODE low with VDDS high). Refer to “Section 6.2”. 6. The battery responds to an LTC1760 Master read of ChargingVoltage() with a non zero voltage request value. 8.
LTC1760 OPERATION This cached bit will remain set if a subsequent AlarmWarning() fails to respond. The cached alarm will be cleared by any of the following conditions. a) Associated battery is removed. b) A subsequent AlarmWarning() clears all charge alarm bits for the associated battery. c) A power on reset event. d) The SMBus Host asserts BatterySystemStateCont(CHARGER_POR) high. 7. The SMBus Host asserts BatterySystemStateCont(CHARGING_INHIBIT) high. 8.
LTC1760 OPERATION a) The programmed current cannot exceed the maximum of the two requested currents + ILIMIT. This relaxed limit enables accelerated charging if ILIMIT is greater than the maximum of the two requested currents. For the recommended matched battery pair the requested current should be the same. b) The programmed current cannot exceed ILIMIT TURBO mode provides a mechanism for the SMBus Host to enable the charge MUX to apply additional current to both batteries.
LTC1760 OPERATION 2. A battery issues a TERMINATE_DISCHARGE alarm and AC_PRESENT is low. The LTC1760 will select the other battery to power the system. 3. A battery issues a TERMINATE_DISCHARGE alarm, AC_PRESENT is low, and the other battery is not present or has previously issued an alarm. The LTC1760 will autonomously try to restore power by entering 3-Diode mode. The 3-Diode mode will ignore TERMINATE_DISCHARGE and FULLY_DISCHARGED alarms. 4.
LTC1760 OPERATION 0000b: Clears CALIBRATE_BAT1 and CALIBRATE_BAT2 and allows LTC1760 to chose. Power on reset default. May not be updated if a calibration is in progress. Option 2) SMBus Host allows LTC1760 to choose battery to be calibrated. BatterySystemStateCont(CALIBRATE_BAT[4:1]) = 0000b. See previous option. The LTC1760 determines that the battery requires calibration by reading BatteryMode(CONDITION_FLAG). This flag is cached in the LTC1760.
LTC1760 OPERATION SMBALERT is used to monitor charging status of Battery 1. Allowed values are: Low: Battery 1 is charging. High: Battery 1 not charging (AC is not present or battery is not present). Blinking: Battery 1 charge complete (AC is present, battery is present and not charging). SCL is an input and is used to determine the blinking rate of SDA and SMBALERT. Tie SCL high if blinking is not desired.
LTC1760 OPERATION is turned off. As VIN decreases towards the selected battery voltage, the converter will attempt to turn on the top MOSFET continuously (“dropout’’). A dropout timer detects this condition and forces the top MOSFET to turn off, and the bottom MOSFET on, for about 200ns at 40μs intervals to recharge the bootstrap capacitor. 7.1 Charge MUX Switches The equivalent circuit of a charge MUX switch driver is shown in Figure 5.
LTC1760 OPERATION (POWER_NOT_GOOD) is set. Similarly, if the voltage at SCN falls below 3V for more than 15ms, then all of the PowerPath switches are turned off and POWER_ NOT_GOOD is set high. The POWER_NOT_GOOD bit is reset by removing all power sources and allowing the voltage at VPLUS to fall below the UVLO threshold. If the POWER_NOT_GOOD bit is set, charging is disabled until VPLUS exceeds the UVLO threshold and the Charger Algorithm allows charging to resume.
LTC1760 OPERATION The delta-sigma modulator and switch SWV convert the VDAC value to a variable resistance equal to (11/8)RVSET/ (VDAC(VALUE)/2047). In regulation, VSET is servo driven to the 0.8V reference voltage, VREF. Capacitors CB1 and CB2 are used to average the voltage present at the VSET pin as well as provide a zero in the voltage loop to help stability and transient response time to voltage variations.
LTC1760 APPLICATIONS INFORMATION Automatic Current Sharing In a dual parallel charge configuration, the LTC1760 does not actually control the current flowing into each individual battery. The capacity, or Amp-Hour rating, of each battery determines how the charger current is shared. This automatic steering of current is what allows both batteries to reach their full capacity points at the same time. In other words, given all other things equal, charge termination will happen simultaneously.
LTC1760 APPLICATIONS INFORMATION As is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see Figure 9 & Table 1). value at all times. Changing the current setting can result in currents that greatly exceed the requested value and potentially damage the battery or overload the wall adapter if no input current limiting is provided. Table 1.
LTC1760 APPLICATIONS INFORMATION CA1. Remember the maximum ΔIL occurs at the maximum input voltage. In practice 10μH is the lowest value recommended for use. Charger Switching Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with the LTC1760 charger: An N-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the VCC voltage. This voltage is typically 5.2V.
LTC1760 APPLICATIONS INFORMATION For thermistors that are IDEAL-RANGE: ISAFETYX = 4/64 • VVCC2/(RXB + RTHX) + 2/64 • VVCC2/ (R1A +RTHX) For thermistors that are HOT-RANGE: ISAFETYX = 4/64 • VVCC2/(RXB + RTHX) + 4/64 • VVCC2/ (R1A +RTHX) RTHX is the impedance of the battery’s thermistor to ground. RXB = 54.9k IDCIN_CHG = ICH1 + IVCC2_AC1 + ISAFETY1 + ISAFETY2 + IVLIM + IILIM + ISMB + ISMB_BAT1 + ISMB_BAT2 + ISMBALERT = 1.3mA + 700μA + 218μA + 218μA +81μA + 81μA + 0μA + 5.4μA + 5.4μA + 0μA = 2.
LTC1760 APPLICATIONS INFORMATION Calculating IC Power Dissipation The power dissipation of the LTC1760 is dependent upon the gate charge of QTG and QBG.(Refer to Typical Application). The gate charge is determined from the manufacturer’s data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the FET. PD = (VDCIN – VVCC) • fOSC • (QTG + QBG) + VDCIN • IDCIN_CHG – VVCC • (ISAFETY1 + ISAFETY2) where: IDCIN_CHG, ISAFETY1, ISAFETY2 are defined in the previous section.
LTC1760 APPLICATIONS INFORMATION The relatively high ESR of an aluminum electrolytic for C15, located at the AC adapter input terminal, is helpful in reducing ringing during the hot-plug event. Refer to AN88 for more information. Highest possible voltage rating on the capacitor will minimize problems. Consult with the manufacturer before use. Alternatives include new high capacity ceramic (at least 20μF) from Tokin, United Chemi-Con/Marcon, et al.
LTC1760 APPLICATIONS INFORMATION The LTC1760 has two transient conditions that force the discharge path P-channel MOSFETs to have two additional parameters to consider. The parameters are gate charge QGATE and single pulse power capability. When the LTC1760 senses a LOW_POWER event, all the P-channel MOSFETs are turned on simultaneously to allow voltage recovery due to a loss of a given power source. However, there is a delay in the time it takes to turn on all the MOSFETs.
LTC1760 APPLICATIONS INFORMATION A) Single Battery Configuration. 4) Reduce CIN capacitor to 0.1μF. To limit the LTC1760 to a single battery, modify the battery slot to be eliminated as follows: 5) Remove all components connected to COMP1, VSET, ITH, ISET, ILIMIT and VLIMIT pins. 1) Remove both FETs (Q5, Q6 or Q7, Q8) involved in the discharge path. 2) Remove both FETS (Q3, Q4 or Q9, Q10) involved in the charge path. 3) Remove the thermistor sensing resistors (R1A, R1B or R2A, R2B).
LTC1760 APPLICATIONS INFORMATION 2. The control IC needs to be close to the switching FET’s gate terminals. Keep the gate drive signals short for a clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be placed on the opposite side of the PCB relative to above. 3. Place inductor input as close as possible to switching FET’s output connection. Minimize the surface area of this trace.
LTC1760 TYPICAL APPLICATIONS PowerPath MUX RCL 0.03Ω VIN R4 12.7k 100pF R5 1.21k R7 49.9k C11 1800pF C3 0.012μF VDDS SMBALERT RPU RPU SDA VDDS C1 0.1μF C9 0.1μF C1 0.1μF R1 4.
LTC1760 PACKAGE DESCRIPTION FW Package 48-Lead Plastic TSSOP (6.1mm) (Reference LTC DWG # 05-08-1651) 48 12.40 – 12.60* (.488 – .496) 25 0.95±0.10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 8.1±0.10 6.2±0.10 7.9 – 8.3 (.311 – .327) 1 24 0.32±0.05 0.50 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RECOMMENDED SOLDER PAD LAYOUT 6.0 – 6.2** (.236 – .244) 1.10 (.0433) MAX 0.25 REF 0–8 -T0.10 C -C0.09 – 0.20 (.0035 – .008) 0.45 – 0.75 (.018 – .
LTC1760 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 04/11 I-Grade part added. Reflected throughout the data sheet 1-48 1760fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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