Datasheet

8
LTC1754-3.3/LTC1754-5
Layout Considerations
Due to high switching frequency and high transient cur-
rents produced by the LTC1754, careful board layout is
necessary. A true ground plane and short connections to
all capacitors will improve performance and ensure proper
regulation under all conditions. Figure 4 shows the recom-
mended layout configuration
Figure 4. Recommended Layout
signal will keep V
OUT
in regulation under no-load condi-
tions. As the V
OUT
load current increases, the frequency
with which the LTC1754 is taken out of shutdown must
also be increased.
Figure 2. Ultralow Quiescent Current Regulated Supply
Figure 3. No-Load Supply Current vs Supply Voltage
for the Circuit Shown in Figure 2
SUPPLY VOLTAGE (V)
2.0
SUPPLY CURRENT (µA)
4
5
6
3.5 4.5
1754 F03
3
2
2.5 3.0
4.0 5.0 5.5
1
0
T
A
= 25°C
I
OUT
= 0µA
C
FLY
= 1µF
LTC1754-5
LTC1754-3.3
LTC1754-X
V
IN
V
OUT
GND
1754-5 F04
SHDN
10µF 10µF
1µF
C
+
1
2
3
6
5
4
LTC1754-X
V
IN
C
–
V
OUT
1754 F02
V
IN
V
OUT
LOW I
Q
MODE (2Hz TO 100Hz, 2% TO 5% DUTY CYCLE)
10µF
1µF
10µF
SHDN PIN
WAVEFORM
GND
SHDN
Thermal Management
For higher input voltages and maximum output current,
there can be substaintial power dissipation in the LTC1754.
If the junction temperature increases above approximately
150°C, the thermal shutdown circuitry will automatically
deactivate the output. To reduce the maximum junction
temperature, a good thermal connection to the PC board
is recommended. Connecting the GND pin (Pin 2) to a
ground plane and maintaining a solid ground plane under
the device on at least two layers of the PC board can reduce
the thermal resistance of the package and PC board
system to about 150°C/W.
APPLICATIO S I FOR ATIO
WUUU