Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 48

LTC1744

1744f

14-Bit, 50Msps ADC

■

Sample Rate: 50Msps

■

77dB SNR and 87dB SFDR (3.2V Range)

■

73.5dB SNR and 90dB SFDR (2V Range)

■

No Missing Codes

■

Single 5V Supply

■

Power Dissipation: 1.2W

■

Selectable Input Ranges: ±1V or ±1.6V

■

150MHz Full Power Bandwidth S/H

■

Pin Compatible Family

25Msps: LTC1746 (14 Bit), LTC1745 (12 Bit)

50Msps: LTC1744 (14 Bit), LTC1743 (12 Bit)

65Msps: LTC1742 (14 Bit), LTC1741 (12 Bit)

80Msps: LTC1748 (14 Bit), LTC1747 (12 Bit)

■

48-Pin TSSOP Package

■

Telecommunications

■

Receivers

■

Base Stations

■

Spectrum Analysis

■

Imaging Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

14-BIT

PIPELINED ADC

S/H

CIRCUIT

±1V

DIFFERENTIAL

ANALOG INPUT

–

SENSE

4.7µF

DIFF AMP

REFLA REFHB

GND

1744 BD

ENC

4.7µF

0.1µF0.1µF

1µF1µF

REFHAREFLB

BUFFER

RANGE

SELECT

2.5V

REF

CORRECTION

LOGIC AND

SHIFT

OUTPUT

LATCHES

CONTROL LOGIC

OGND

0.5V TO 5V

0.1µF

1µF 1µF 1µF

D13

CLKOUT

•

ENC

DIFFERENTIAL

ENCODE INPUT

OEMSBINV

0.1µF

The LTC

1744 is a 50Msps, sampling 14-bit A/D con-

verter designed for digitizing high frequency, wide dynamic

range signals. Pin selectable input ranges of ±1V and ±1.6V

along with a resistor programmable mode allow the

LTC1744’s input range to be optimized for a wide variety

of applications.

The LTC1744 is perfect for demanding communications

applications with AC performance that includes 77dB

SNR and 87dB spurious free dynamic range. Ultralow jitter

of 0.3ps

RMS

allows undersampling of IF frequencies with

excellent noise performance. DC specs include ±4LSB

maximum INL and no missing codes over temperature.

The digital interface is compatible with 5V, 3V and 2V logic

systems. The ENC and ENC inputs may be driven differen-

tially from PECL, GTL and other low swing logic families or

from single-ended TTL or CMOS. The low noise, high gain

ENC and ENC inputs may also be driven by a sinusoidal

signal without degrading performance. A separate output

power supply can be operated from 0.5V to 5V, making it

easy to connect directly to any low voltage DSPs or FIFOs.

The TSSOP package with a flow-through pinout simplifies

the board layout.

50Msps, 14-Bit ADC with a ±1V Differential Input Range

DESCRIPTIO

FEATURES

APPLICATIO S

BLOCK DIAGRA

Summary of content (24 pages)

PAGE 1
LTC1744 14-Bit, 50Msps ADC U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC ®1744 is a 50Msps, sampling 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. Pin selectable input ranges of ±1V and ±1.6V along with a resistor programmable mode allow the LTC1744’s input range to be optimized for a wide variety of applications. Sample Rate: 50Msps 77dB SNR and 87dB SFDR (3.2V Range) 73.
PAGE 2
LTC1744 W U PACKAGE/ORDER INFORMATION U W W W OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................ 6V Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ..... – 0.3V to (VDD + 0.3V) Digital Output Voltage ................. – 0.3V to (VDD + 0.3V) OGND Voltage ..............................................– 0.3V to 1V Power Dissipation ............................................
PAGE 3
LTC1744 W U DY A IC ACCURACY The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input Signal (2V Range) 5MHz Input Signal (3.2V Range) SFDR S/(N + D) THD IMD Spurious Free Dynamic Range MIN TYP 75.5 73.5 77 dBFS dBFS 25MHz Input Signal (2V Range) 25MHz Input Signal (3.2V Range) 72.5 75.
PAGE 4
LTC1744 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.75V IIN Digital Input Current VIN = 0V to VDD CIN Digital Input Capacitance MSBINV and OE Only VOH High Level Output Voltage OVDD = 4.75V VOL Low Level Output Voltage OVDD = 4.
PAGE 5
LTC1744 U W TYPICAL PERFOR A CE CHARACTERISTICS Typical INL, 3.2V Range 2.0 Nonaveraged, 8192 Point FFT, Input Frequency = 2.5MHz, –1dB, 2V Range Typical DNL, 3.2V Range 1.0 TA = 25°C 0.5 TA = 25°C 0.8 1.5 –20.0 0 –0.5 –1.0 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) –30.0 0.5 0.2 0 –0.2 –0.4 –1.5 0 4000 8000 CODE 12000 –1.0 16000 1744 G01 –60.0 –70.0 –80.0 –110.0 0 4000 8000 CODE 12000 –120.0 16000 1744 G03 Nonaveraged, 8192 Point FFT, Input Frequency = 2.5MHz, –1dB, 3.2V Range 0.
PAGE 6
LTC1744 U W TYPICAL PERFOR A CE CHARACTERISTICS Averaged, 8192 Point FFT, Input Frequency = 2.5MHz, – 6dB, 3.2V Range 0.5 0.5 –10.0 Averaged, 8192 Point FFT, Input Frequency = 2.5MHz, – 20dB, 3.2V Range 0.5 TA = 25°C –10.0 –20.0 –20.0 –30.0 –30.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 AMPLITUDE (dBFS) –20.0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) Averaged, 8192 Point FFT, Input Frequency = 2.5MHz, – 20dB, 2V Range TA = 25°C –10.0 (Note 5) –40.0 –50.0 –60.0 –70.0 –80.0 –40.0 –50.0 –60.0 –70.0 –80.
PAGE 7
LTC1744 U W TYPICAL PERFOR A CE CHARACTERISTICS Averaged, 8192 Point FFT, Input Frequency = 51MHz, – 20dB, 2V Range 0.5 0.5 Averaged, 8192 Point FFT, Input Frequency = 70MHz, – 6dB, 2V Range 0.5 TA = 25°C –10.0 –20.0 –30.0 –30.0 –50.0 –60.0 –70.0 –80.0 AMPLITUDE (dBFS) –20.0 –30.0 –40.0 –40.0 –50.0 –60.0 –70.0 –80.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 –90.0 –90.0 –100.0 –100.0 –100.0 –110.0 –110.0 –110.0 –120.0 –120.0 0 2 4 6 8 10 12 14 16 18 20 22 24 25.37 FREQUENCY (MHz) –120.
PAGE 8
LTC1744 U W TYPICAL PERFOR A CE CHARACTERISTICS 120 120 TA = 25°C SFDR (dBFS) – 6dBFS 90 80 3rd HARMONIC –70 100 – 6dBFS 90 –1dBFS 80 –1dBFS 70 60 10 INPUT FREQUENCY (MHz) 60 100 1 10 INPUT FREQUENCY (MHz) 100 –60 TA = 25°C –60 TA = 25°C –90 1 10 INPUT FREQUENCY (MHz) –80 –90 –100 100 –120 –80 –90 –110 1 10 INPUT FREQUENCY (MHz) 100 1744 G26 1 10 INPUT FREQUENCY (MHz) 100 1744 G27 1744 G29 SFDR vs Input Amplitude, 2V Range, 5MHz Input Frequency 110 TA = 25°C –100 –11
PAGE 9
LTC1744 U W TYPICAL PERFOR A CE CHARACTERISTICS Input = 5MHz, –25dBFS, Dither Applied TA = 25°C AMPLITUDE (dB) AMPLITUDE (dB) Input = 5MHz, –25dBFS, No Dither 0.5 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 0 2 4 6 8 10 12 14 16 18 20 22 24 24.99 FREQUENCY (MHz) 1744 G36 (Note 5) 0.5 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 TA = 25°C 0 2 4 6 8 10 12 14 16 18 20 22 24 24.
PAGE 10
LTC1744 WU W TI I G DIAGRA N ANALOG INPUT t3 t2 t1 ENCODE t6 t4 DATA t5 DATA (N – 3) DB13 TO DB0 DATA (N – 4) DB13 TO DB0 DATA (N – 5) DB13 TO DB0 t5 CLKOUT t7 t8 OE DATA N DB13 TO DB0, OF AND CLKOUT DATA 1744 TD W FU CTIO AL BLOCK DIAGRA U U OVDD 0.1µF AIN+ ±1V DIFFERENTIAL ANALOG INPUT S/H CIRCUIT AIN– CORRECTION LOGIC AND SHIFT REGISTER 14-BIT PIPELINED ADC 14 OUTPUT LATCHES • • • 0.5V TO 5V 0.
PAGE 11
LTC1744 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S / (N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
PAGE 12
LTC1744 U U W U APPLICATIO S I FOR ATIO The LTC1744 has two phases of operation, determined by the state of the differential ENC/ENC input pins. For brevity, the text will refer to ENC greater than ENC as ENC high and ENC less than ENC as ENC low. the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage.
PAGE 13
LTC1744 U U W U APPLICATIO S I FOR ATIO the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.
PAGE 14
LTC1744 U U W U APPLICATIO S I FOR ATIO Input Drive Circuits Figure 3 shows the LTC1744 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedence seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response.
PAGE 15
LTC1744 U U W U APPLICATIO S I FOR ATIO An external bypass capacitor of 4.7µF or larger is required for the 2.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference. It will not be stable without this capacitor. Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 6a.
PAGE 16
LTC1744 U U W U APPLICATIO S I FOR ATIO Input Range Driving the Encode Inputs The input range can be set based on the application. For oversampled signal processing in which the input frequency is low (<10MHz), the largest input range will provide the best signal-to-noise performance while maintaining excellent SFDR. For high input frequencies (>10MHz), the 2V range will have the best SFDR performance but the SNR will degrade by 3.5dB. See the Typical Performance Characteristics section.
PAGE 17
LTC1744 U W U U APPLICATIO S I FOR ATIO Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3.
PAGE 18
LTC1744 U W U U APPLICATIO S I FOR ATIO DIGITAL OUTPUTS Lower OVDD voltages will also help reduce interference from the digital outputs. Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages.
PAGE 19
LTC1744 U W U U APPLICATIO S I FOR ATIO Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 3V supply then OVDD should be tied to that same 3V supply. OVDD can be powered with any voltage up to 5V.
PAGE 20
C1 4.7µF • • C29 TBD R21 100Ω • R23 3k • R11 50Ω T2 MINICIRCUITS T1-1T R3 100Ω E3 GND E4 GND E5 GND R2 37Ω R1** 0Ω R9** 10Ω C11 1µF 5V R22 100Ω JP3 C5 18pF C9 0.15µF C26 0.15µF C14 0.15µF JP4 R5 1Ω 5V R Y* R X* C3 10µF C27 C15 0.15µF 0.15µF C7 0.15µF C18 4.7µF C13 0.15µF C6 2.2µF C24** 18pF INPUT TWO RANGE COMPLEMENT SELECT SELECT C8 4.7µF C25** 18pF R10** 0Ω R7 37Ω R4 100Ω R24 2k C2 4.
PAGE 21
LTC1744 U W U U APPLICATIO S I FOR ATIO Topside Silkscreen Topside Copper Layer Ground Plane, Layer 2 1744f 21
PAGE 22
LTC1744 U W U U APPLICATIO S I FOR ATIO Split Power Plane, Layer 3 Bottom Side Copper, Layer 4 1744f 22
PAGE 23
LTC1744 U PACKAGE DESCRIPTIO FW Package 48-Lead Plastic TSSOP (6.1mm) (Reference LTC DWG # 05-08-1651) 12.4 – 12.6* (.488 – .496) 0.95 ±0.10 8.1 ±0.10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 6.2 ±0.10 7.9 – 8.3 (.311 – .327) 0.32 ±0.05 0.50 TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RECOMMENDED SOLDER PAD LAYOUT 1.20 (.0473) MAX 6.0 – 6.2** (.236 – .244) 0° – 8° -T.10 C -C0.09 – 0.20 (.0035 – .008) 0.45 – 0.75 (.018 – .029) 0.50 (.
PAGE 24
LTC1744 RELATED PARTS PART NUMBER ® DESCRIPTION COMMENTS LT 1019 Precision Bandgap Reference 0.05% Max Initial Accuracy, 5ppm/°C Max Drift LTC1196 8-Bit, 1Msps ADC 3V to 5V, SO-8 LTC1405 12-Bit, 5Msps, Sampling ADC with Parallel Output Pin Compatible with the LTC1420 LTC1406 8-Bit, 20Msps ADC Undersampling Capability Up to 70MHz Input LTC1411 14-Bit, 2.5Msps ADC No Pipeline Delay, 5V, 80dB SINAD LTC1410 12-Bit, 1.