Datasheet

11
LTC1707
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1707. These items are also illustrated graphically in
the layout diagram of Figure 7. Check the following in your
layout:
1. Are the signal and power grounds segregated? The
LTC1707 signal ground consists of the resistive
divider, the optional compensation network (R
C
and
C
C1
), C
SS
, C
REF
and C
C2
. The power ground consists of
the (–) plate of C
IN
, the (–) plate of C
OUT
and Pin 4 of the
LTC1707. The power ground traces should be kept
short, direct and wide. The signal ground and power
ground should converge to a common node in a star-
ground configuration.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and signal ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node SW away from sensitive small-
signal nodes.
Figure 7. LTC1707 Layout Diagram
C
C2
C
C1
R
C
OPTIONAL
C
SS
C
OUT
C
IN
L1
R1
BOLD LINES INDICATE HIGH CURRENT PATHS
1
2
3
4
8
7
6
5
V
REF
SYNC/MODE
V
IN
SW
I
TH
RUN/SS
V
FB
GND
LTC1707
R2
V
IN
1707 F07
+
–
V
OUT
+
–
C
REF
+
+
APPLICATIO S I FOR ATIO
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