Datasheet

LTC1665/LTC1660
8
166560fa
BLOCK DIAGRAM
PIN FUNCTIONS
GND (Pin 1): System Ground.
V
OUT A
to V
OUT H
(Pins 2-5 and 12-15): DAC Analog Volt-
age Outputs. The output range is
0to
255
256
⎛
⎝
⎜
⎞
⎠
⎟
V
REF
for the LTC1665
0to
1023
1024
⎛
⎝
⎜
⎞
⎠
⎟
V
REF
for the LTC1660
REF (Pin 6): Reference Voltage Input. 0V ≤ V
REF
≤ V
CC
.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
D
IN
into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
D
IN
(Pin 9): Serial Interface Data Input. Data on the D
IN
pin is shifted into the 16-bit register on the rising edge of
SCK. CMOS and TTL compatible.
D
OUT
(Pin 10): Serial Interface Data Output. Data appears
on D
OUT
16 positive SCK edges after being applied to D
IN
.
May be tied to D
IN
of another LTC1665/LTC1660 for daisy-
chain operation. CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
V
CC
(Pin 16): Supply Voltage Input. 2.7V ≤ V
CC
≤ 5.5V.
(LTC1665/LTC1660)
2
15
1GND
V
OUT A
V
OUT B
V
OUT C
V
OUT D
REF
CS/LD
SCK
V
CC
V
OUT H
V
OUT G
V
OUT F
V
OUT E
CLR
D
OUT
D
IN
166560 BD
16
DAC A DAC H
3 14
DAC B DAC G
4 13
DAC C DAC F
5
7
6
8
10
11
9
12
DAC D DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER