Datasheet

LTC1665/LTC1660
10
166560fa
OPERATION
Sleep Mode
DAC address 1110
b
is reserved for the special Sleep instruc-
tion (see Table 2). In this mode, the digital interface stays
active while the analog circuits are disabled; static power
consumption is thus virtually eliminated. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
D
IN
D
OUT
SCK
C
S/LD
A3 A2
INPUT WORD W
0
INPUT CODE
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2
X1 X0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0 A3
166560 F02a
16151413121110987654321
(ENABLE CLK) (UPDATE OUTPUT)
ADDRESS/CONTROL DON’T CARE
INPUT WORD W
0
INPUT WORD W
–1
D
IN
D
OUT
SCK
C
S/LD
A3 A2
INPUT WORD W
0
INPUT CODE DON’T CARE
A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X1 X0
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 A3
166560 F02b
16151413121110987654321
(ENABLE CLK) (UPDATE OUTPUT)
ADDRESS/CONTROL
INPUT WORD W
0
INPUT WORD W
–1
Figure 2a. LTC1665 Register Loading Sequence
Figure 2b. LTC1660 Register Loading Sequence
Table 1a. LTC1665 Input Word
Table 1b. LTC1660 Input Word
A3 A2 A1
ADDRESS/CONTROL
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 X1 X0D0
INPUT CODE DON’T
CARE
A3 A2 A1
ADDRESS/CONTROL
A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X1 X0X2
DON’T CAREINPUT CODE