LTC1664
7
1664fa
Block Diagram
2
5
1GND
V
OUT A
V
OUT B
REF
CS/LD
SCK
V
CC
V
OUT D
V
OUT C
CLR
D
OUT
D
IN
1664 BD
16
10-BIT
DAC A
10-BIT
DAC D
3 4
10-BIT
DAC B
10-BIT
DAC C
7
6
8
10
11
9
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
timing Diagram
D
IN
D
OUT
CS/LD
SCK
A3
A3
A3 A2
A2 X1A1 X0
1664 F01
A1 X1
X0
t
2
t
8
t
9
t
11
t
5
t
7
t
6
t
1
t
3
t
4
Figure 1
