Datasheet

LTC1664
6
1664fa
typical perFormance characteristics
Minimum V
OUT
vs Load Current
(Output Sinking)
Minimum Supply Headroom vs
Load Current (Output Sourcing)
|I
OUT
| (mA) (SINKING)
0 2 4 6 8 10
V
OUT
(mV)
1664 G10
1400
1200
1000
800
600
400
200
0
–55°C
25°C
125°C
V
CC
= 5V
CODE = 0
0 2 4 6 8 10
V
CC
– V
OUT
(mV)
1664 G11
1400
1200
1000
800
600
400
200
0
–55°C
25°C
125°C
V
REF
= 4.096V
∆V
OUT
< 1LSB
CODE = 1023
|I
OUT
| (mA) (SOURCING)
pin Functions
GND (Pin 1): System Ground.
V
OUT A
to V
OUT D
(Pins 2–5): DAC Analog Voltage Outputs.
The output range is:
0 to
1023
1024






V
REF
REF (Pin 6): Reference Voltage Input. 0V ≤ V
REF
≤ V
CC
.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
D
IN
into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
D
IN
(Pin 9): Serial Interface Data Input. Data on the D
IN
pin is shifted into the 16-bit register on the rising edge of
SCK. CMOS and TTL compatible.
D
OUT
(Pin 10): Serial Interface Data Output. Data appears
on D
OUT
16 positive SCK edges after being applied to D
IN
.
May be tied to D
IN
of another serial device for daisy-chain
operation. CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero-scale.
CMOS and TTL compatible.
NC (Pins 12–15): Make no electrical connection to these
pins.
V
CC
(Pin 16): Supply Voltage Input. 2.7V ≤ V
CC
≤ 5.5V.