Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSOT 23 5

LTC1663

1663fd

BLOCK DIAGRAM

FEATURES

APPLICATIONS

DESCRIPTION

10-Bit Rail-to-Rail

Micropower DAC with

2-Wire Interface

The LTC

1663 is a 10-bit voltage output DAC with true

buffered rail-to-rail output voltage capability. It operates

from a single supply with a range of 2.7V to 5.5V. The

reference for the DAC is selectable between the supply

voltage or an internal bandgap reference. Selecting the

internal bandgap reference will set the full-scale output

voltage range to 2.5V. Selecting the supply as the reference

sets the output voltage range to the supply voltage.

The part features a simple 2-wire serial interface compat-

ible with SMBus that allows communication between many

devices. The internal data registers are double buffered to

allow for simultaneous update of several devices at once.

The DAC can be put in low current power-down mode for

use in power conscious systems.

Power-on reset ensures the DAC output is at 0V when

power is initially applied, and all internal registers are

cleared.

For I

C designs, please refer to the LTC1669.

Differential Nonlinearity (DNL)

Micropower 10-Bit DAC in SOT-23

Low Operating Current: 60μA

Ultralow Power Shutdown Mode: 10μA

2-Wire Serial Interface Compatible

with SMBus

Selectable Internal Reference or Ratiometric to

Maximum DNL Error: 0.75LSB

8 User Selectable Addresses (MSOP Package)

Single 2.7V to 5.5V Operation

Buffered True Rail-to-Rail Voltage Output

Power-On Reset

0.6V V

and 1.4V V

for SDA and SCL

Small 5-Lead SOT-23 and 8-Lead MSOP Packages

Digital Calibration

Offset/Gain Adjustment

Industrial Process Control

Automatic Test Equipment

Arbitrary Function Generators

Battery-Powered Data Conversion Products

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

10-BIT

DAC LATCH

INPUT

LATCH

2-WIRE INTERFACE

SDA

AD0

(6)

MSOP

PACKAGE

ONLY

(2)

(3)

AD1

AD2

SCL

1 (1) 5 (4)

GND

2 (7)

OUT

3 (8)

1663 BD

1.25V

4 (5)

BANDGAP

REFERENCE

SELECT

–

COMMAND

LATCH

NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE

CODE

–1.0

ERROR (LSB)

–0.8

–0.4

–0.2

1.0

0.4

156

512

640

1663 TA01

–0.6

0.6

0.8

0.2

28 384

768

896

1024

REF

= V

= 5V

= 25°C

Summary of content (12 pages)

PAGE 1
LTC1663 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface DESCRIPTION FEATURES n n n n n n n n n n n n Micropower 10-Bit DAC in SOT-23 Low Operating Current: 60μA Ultralow Power Shutdown Mode: 10μA 2-Wire Serial Interface Compatible with SMBus Selectable Internal Reference or Ratiometric to VCC Maximum DNL Error: 0.75LSB 8 User Selectable Addresses (MSOP Package) Single 2.7V to 5.5V Operation Buffered True Rail-to-Rail Voltage Output Power-On Reset 0.6V VIL and 1.
PAGE 2
LTC1663 ABSOLUTE MAXIMUM RATINGS (Note 1) VCC to GND .............................................. – 0.3V to 7.5V SDA, SCL ................................................. –0.3V to 7.5V AD0, AD1, AD2 (MSOP Only) ........–0.3V to (VCC + 0.3V) VOUT .............................................–0.3V to (VCC + 0.3V) Storage Temperature Range.................. –65°C to 150°C Operating Temperature Range LTC1663C ............................................... 0°C to 70°C LTC1663I.............................
PAGE 3
LTC1663 ELECTRICAL CHARACTERISTICS The ● denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN VCC Positive Supply Voltage l ICC Supply Current VCC = 3V (Note 3) VCC = 5V (Note 3) l l ISD Supply Current in Shutdown Mode (Note 3) LTC1663E (Note 3) Short-Circuit Current (Sourcing) TYP MAX 2.7 UNITS 5.
PAGE 4
LTC1663 TIMING CHARACTERISTICS The ● denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER MIN tSU, DAT Data Setup Time ● 250 tLOW Clock Low Period ● 4.7 tHIGH Clock High Period ● 4.0 tf Clock, Data Fall Time tr Clock, Data Rise Time TYP MAX UNITS ns μs 50 μs ● 300 ns ● 1000 ns Note 5: VCC = VREF = 5V.
PAGE 5
LTC1663 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error Voltage vs Temperature Load Regulation vs Output Current OFFSET ERROR VOLTAGE (mV) 0.6 VCC = VREF = 3V VOUT = 1.5V CODE = 512 TA = 25°C ΔVOUT (LSB) 0.4 0.2 0 –0.2 –0.4 SOURCE SINK 5 2.510 4 2.508 3 2.506 OUTPUT VOLTAGE (V) 1.0 0.8 Full-Scale Output Voltage vs Temperature 2 1 0 –1 –2 2.504 2.502 2.500 2.498 2.496 –3 2.494 –0.8 –4 2.492 –1.0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.
PAGE 6
NOTE: X = DON’T CARE 2 1 SCL 3 0 0 4 0 0 5 1 AD2 ADDRESS 6 1 AD1 tr tHIGH tf tSU, DAT tHD, DAT REPEATED START CONDITION tSU, STA tHD, STA STOP CONDITION tBUF tSU, STO START CONDITION 1663 TD 7 1 AD0 8 0 WR 9 ACK 1 X X 2 X X 3 X X 4 X X 5 X X COMMAND 6 0 BG 7 0 SD 8 0 SY 9 ACK 1 1 D7 2 1 D6 3 1 D5 4 1 5 1 D3 LS DATA D4 6 1 D2 7 1 D1 8 1 D0 9 ACK 1 X X 2 X X 3 X X 4 X X 5 X X MS DATA 6 X X 7 1 D9 8
PAGE 7
LTC1663 DEFINITIONS Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code that guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: Resolution (n): Deﬁnes the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity.
PAGE 8
LTC1663 APPLICATIONS INFORMATION Bit (Wr) = 0. The LTC1663 acknowledges and the master delivers the command byte. The LTC1663 acknowledges and latches the command byte into the command byte input register. The master then delivers the least signiﬁcant data byte. Again the LTC1663 acknowledges and the data is latched into the least signiﬁcant data byte input register. The master then delivers the most signiﬁcant data byte.
PAGE 9
LTC1663 APPLICATIONS INFORMATION Data Bytes Least Signiﬁcant Data Byte 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 The SY/CLR bit set high only has meaning when the “SY” bit of the command byte was previously set HIGH. On the otherhand, the SY/CLR bit set LOW will always clear the part, independent of the state of the “SY” bit in the command byte.
PAGE 10
LTC1663 APPLICATIONS INFORMATION POSITIVE FSE VREF = VCC OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 512 INPUT CODE (a) 1023 OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1663 F01 Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve.
PAGE 11
LTC1663 PACKAGE DESCRIPTION S5 Package 5-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1635) 0.62 MAX 0.95 REF 2.90 BSC (NOTE 4) 1.22 REF 2.80 BSC 1.4 MIN 3.85 MAX 2.62 REF 1.50 – 1.75 (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 TYP 5 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4.
PAGE 12
LTC1663 TYPICAL APPLICATION Program Up to 8 Control Outputs Per BUS (8 LTC1663 and 8 LTC1663-8 DACs) and Place Them Where They Are Needed VCC = 2.7V TO 5.5V μP SDA SCL 5 4 + 5 4 VCC SCL 1 SDA 8 LTC1663-8CMS8 6 VOUT AD0 2 AD1 3 AD2 GND + 0.1μF SMBus 2 GND 2 + 5 4 VCC SCL 1 SDA 8 LTC1663CMS8 6 VOUT AD0 2 AD1 3 AD2 GND 0.1μF CONTROL OUTPUT 0 0V ≤ VOUT0 < VCC 7 0.