Datasheet

6
LTC1661
PIN FUNCTIONS
UUU
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on D
IN
into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the Control
code, A3-A0, is (are) performed. CMOS and TTL compat-
ible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
D
IN
(Pin 3): Serial Interface Data Input. Input word data on
the D
IN
pin is shifted into the 16-bit register on the rising
edge of SCK. CMOS and TTL compatible.
REF (Pin 4): Reference Voltage Input. 0V ≤ V
REF
≤ V
CC
.
V
OUT A
, V
OUT B
(Pins 8,5): DAC Analog Voltage Outputs.
The output range is
0
1023
1024
≤≤






VV V
OUTA OUTB REF
,
V
CC
(Pin 6): Supply Voltage Input. 2.7V ≤ V
CC
≤ 5.5V.
GND (Pin 7): System Ground.
DEFINITIONS
UU
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/1023)]/LSB
Where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = V
REF
/1024
Resolution (n): Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆V
OUT
– LSB)/LSB
Where ∆V
OUT
is the measured voltage difference between
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is calculated
as follows: