Datasheet

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LTC1661

Micropower Dual

10-Bit DAC in MSOP

The LTC

1661 integrates two accurate, serially addres-

sable, 10-bit digital-to-analog converters (DACs) in a

single tiny MS8 package. Each buffered DAC draws just

60µA total supply current, yet is capable of supplying DC

output currents in excess of 5mA and reliably driving

capacitive loads up to 1000pF. Sleep mode further re-

duces total supply current to a negligible 1µA.

Linear Technology’s proprietary, inherently monotonic

voltage interpolation architecture provides excellent lin-

earity while allowing for an exceptionally small external

form factor. The double-buffered input logic provides

simultaneous update capability and can be used to write to

either DAC without interrupting Sleep mode.

Ultralow supply current, power-saving Sleep mode and

extremely compact size make the LTC1661 ideal for

battery-powered applications, while its straightforward

usability, high performance and wide supply range make

it an excellent choice as a general purpose converter.

For additional outputs and even greater board density,

please refer to the LTC1660 micropower octal DAC for

10-bit applications. For 8-bit applications, please consult

the LTC1665 micropower octal DAC.

■

Tiny: Two 10-Bit DACs in an 8-Lead MSOP—

Half the Board Space of an SO-8

■

Micropower: 60µA per DAC

Sleep Mode: 1µA for Extended Battery Life

■

Rail-to-Rail Voltage Outputs Drive 1000pF

■

Wide 2.7V to 5.5V Supply Range

■

Double Buffered for Independent or Simultaneous

DAC Updates

■

Reference Range Includes Supply for Ratiometric

0V-to-V

Output

■

Reference Input Has Constant Impedance over All

Codes (260kΩ Typ)—Eliminates External Buffers

■

3-Wire Serial Interface with

Schmitt Trigger Inputs

■

Differential Nonlinearity: ≤±0.75LSB Max

, LTC and LT are registered trademarks of Linear Technology Corporation.

CS/LD

1661 BD

1 4

10-BIT

DAC A

10-BIT

DAC B

ADDRESS

DECODER

CONTROL

LOGIC

SHIFT REGISTER

SCK

REF

OUT

8 5

GND

OUT

LATCH

Differential Nonlinearity (DNL)

■

Mobile Communications

■

Digitally Controlled Amplifiers and Attenuators

■

Portable Battery-Powered Instruments

■

Automatic Calibration for Manufacturing

■

Remote Industrial Devices

APPLICATIO S

FEATURES

DESCRIPTIO

BLOCK DIAGRA

CODE

0 256 512 768 1023

LSB

1661 G02

0.75

–0.75

0.60

0.40

0.20

–0.20

–0.40

–0.60

Summary of content (12 pages)

PAGE 1
LTC1661 Micropower Dual 10-Bit DAC in MSOP U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ Tiny: Two 10-Bit DACs in an 8-Lead MSOP— Half the Board Space of an SO-8 Micropower: 60µA per DAC Sleep Mode: 1µA for Extended Battery Life Rail-to-Rail Voltage Outputs Drive 1000pF Wide 2.7V to 5.
PAGE 2
LTC1661 W W W AXI U U ABSOLUTE RATI GS (Note 1) VCC to GND .............................................. – 0.3V to 7.5V Logic Inputs to GND ................................ – 0.3V to 7.5V VOUT A, VOUT B, REF to GND ............ – 0.3V to VCC + 0.3V Maximum Junction Temperature ......................... 125°C Storage Temperature Range ................ – 65°C to 150°C Operating Temperature Range LTC1661C ............................................. 0°C to 70°C LTC1661I ..............................
PAGE 3
LTC1661 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT Unloaded unless otherwise noted.
PAGE 4
LTC1661 WU TI I G CHARACTERISTICS Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10kΩ in parallel with 100pF. Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS, i.e., codes k = 102 and k = 922. Note 6: Guaranteed by design and not subject to test. U W TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (INL) 1400 0.75 2.0 0.60 1.5 VREF = 4.096V ∆VOUT < 1LSB CODE = 1023 1200 0.40 1.0 VCC – VOUT (mV) 1000 0.20 LSB 0.
PAGE 5
LTC1661 U W TYPICAL PERFOR A CE CHARACTERISTICS Load Regulation vs Output Current Load Regulation vs Output Current 2 2 VCC = VREF = 5V CODE = 512 1.5 1.5 1 VCC = VREF = 3V CODE = 512 VCC = VREF = 5V 10% TO 90% STEP CODE = 922 4 1 0 –0.5 0.5 0 –0.5 –1 –1 –1.5 –1.5 SOURCE –2 SINK VOUT (V) 0.
PAGE 6
LTC1661 U U U PIN FUNCTIONS CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, SCK is disabled and the operation(s) specified in the Control code, A3-A0, is (are) performed. CMOS and TTL compatible. SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 3): Serial Interface Data Input.
PAGE 7
LTC1661 U OPERATIO where k is the decimal equivalent of the binary DAC input code D9-D0 and VREF is the voltage at REF (Pin 6). By selecting the appropriate 4-bit Control code (see Table 2) it is possible to perform single operations, such as loading one DAC or changing Power-Down status (Sleep/Wake). In addition, some Control codes perform two or more operations at the same time. For example, one such code loads DAC A, updates both outputs and Wakes the part up.
PAGE 8
LTC1661 U OPERATIO Table 2. DAC Control Functions CONTROL A3 A2 A1 A0 INPUT REGISTER STATUS DAC REGISTER STATUS POWER-DOWN STATUS (SLEEP/WAKE) COMMENTS 0 0 0 0 No Change No Update No Change No Operation. Power-Down Status Unchanged (Part Stays In Wake or Sleep Mode) 0 0 0 1 Load DAC A No Update No Change Load Input Register A with Data. DAC Outputs Unchanged. Power-Down Status Unchanged 0 0 1 0 Load DAC B No Update No Change Load Input Register B with Data.
PAGE 9
LTC1661 U OPERATIO Voltage Outputs Rail-to-Rail Output Considerations Each of the rail-to-rail output amplifiers contained in the LTC1661 can typically source or sink up to 5mA (VCC = 5V). The outputs swing to within a few millivolts of either supply when unloaded and have an equivalent output resistance of 85Ω (typical) when driving a load to the rails. The output amplifiers are stable driving capacitive loads up to 1000pF.
PAGE 10
LTC1661 U TYPICAL APPLICATIO S 0.1µF 5V 4 6 8 DAC A R2 50k R1 5k 10V 0.1µF VA1 = 2.5V CS/LD DIN SCK 3 1 LTC1661 U1 3 FOR EACH U1 AND U2 CODE A CODE B ∆VH, ∆VL 512 1023 –250mV 512 512 0 512 0 250mV VH = 7.5V (FROM MAIN INPUT DAC) 2 2 5 DAC B 8 + U3A LT1368 VH′ = VH + ∆VH 1 0.1µF – 0.1µF 4 R3 50k –5V R4 5k VB1 VH 0.1µF 5V VL 4 6 VOUT LOGIC DRIVE 5 DAC B R6 5k R5 50k 7.5V ±250mV –2.
PAGE 11
LTC1661 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.040 ± 0.006 (1.02 ± 0.15) 0.007 (0.18) 0.118 ± 0.004* (3.00 ± 0.102) 0.034 ± 0.004 (0.86 ± 0.102) 8 7 6 5 0° – 6° TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) BSC 0.021 ± 0.006 (0.53 ± 0.015) 0.118 ± 0.004** (3.00 ± 0.102) 0.193 ± 0.006 (4.90 ± 0.15) 0.006 ± 0.004 (0.15 ± 0.
PAGE 12
LTC1661 U TYPICAL APPLICATIO 5V 4 0.1µF 6 8 DAC A R2 50k R1 5k 10V 0.1µF VA1 = 2.5V CS/LD DIN SCK 3 1 LTC1661 U1 3 FOR EACH U1 AND U2 CODE A CODE B ∆VH, ∆VL 512 1023 –250mV 512 512 0 512 0 250mV VH = 7.5V (FROM MAIN INPUT DAC) 2 2 5 DAC B 8 + U3A LT1368 1 VH′ = VH + ∆VH 0.1µF – 0.1µF 4 R3 50k –5V R4 5k VB1 VH 5V 0.1µF VL 4 6 VOUT LOGIC DRIVE DAC B 5 R6 5k R5 50k 7.5V ±250mV –2.