Datasheet

LTC1659
8
1659fa
OPERATION
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded fi rst.
The DAC register loads the data from the shift register
when
⎯
C
⎯
S/LD is pulled high. The CLK is disabled internally
when
⎯
C
⎯
S/LD is high. Note: CLK must be low before
⎯
C
⎯
S/LD
is pulled low to avoid an extra internal clock pulse.
The buffered output of the 12-bit shift register is available
on the D
OUT
pin which swings from GND to V
CC
. Multiple
LTC1659s may be daisy-chained together by connecting
the D
OUT
pin to the D
IN
pin of the next chip, while the CLK
and
⎯
C
⎯
S/LD signals remain common to all chips in the
daisy chain. The serial data is clocked to all of the chips,
then the
⎯
C
⎯
S/LD signal is pulled high to update all of them
simultaneously.
Voltage Output
The LTC1659’s rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range
while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40Ω when driving a load
to the rails. The output can drive 1000pF without going
into oscillation.
The output swings from 0V to the voltage at the REF pin,
i.e., there is a gain of 1 from the REF to V
OUT
. Please
note if REF is tied to V
CC
the output can only swing to
(V
CC
– V
OS
). See Applications Information.