Datasheet

8
LTC1657/LTC1657L
DIGITAL INTERFACE TRUTH TABLE
U
CLR CSMSB CSLSB WR LDAC FUNCTION
L X X X X Clears input and DAC registers to zero
H X X X L Loads DAC register with contents of input registers
H X X X H Freezes contents of DAC register
H L H L X Writes MSB byte into MSB input register
H H L L X Writes LSB byte into LSB input register
H L L L X Writes MSB and LSB bytes into MSB and LSB input registers
H X X H X Inhibits write to MSB and LSB input registers
H H X X X Inhibits write to MSB input register
H X H X X Inhibits write to LSB input register
H L L L L Data bus flows directly through input and DAC registers
TIMING DIAGRAM
WUW
CSMSB
WR
LDAC
1657 TD
t
CS
CSLSB
DATA
t
CS
t
WR
t
WR
t
CWS
t
CWH
t
DWS
t
LDAC
DAC UPDATE
t
DWH
DATA VALID DATA VALID
UU
U
PI FU CTIO S
CLR (Pin 27): Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all input and DAC
registers to 0s.
LDAC (Pin 28): Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
registers to the DAC register which updates the output
voltage. If held low, the DAC register loads data from the
input registers which will immediately update V
OUT
.