Datasheet

8
LTC1655/LTC1655L
PIN FUNCTIONS
UUU
CLK (Pin 1): The TTL Level Input for the Serial Interface
Clock.
D
IN
(Pin 2): The TTL Level Input for the Serial Interface
Data. Data on the D
IN
pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1655/LTC1655L requires a 16-bit word.
CS/LD (Pin 3): The TTL Level Input for the Serial Inter-
face Enable and Load Control. When CS/LD is low, the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
D
OUT
(Pin 4): Output of the Shift Register. Becomes valid
on the rising edge of the serial clock and swings from GND
to V
CC
.
GND (Pin 5): Ground.
REF (Pin 6): Reference. Output of the internal reference is
2.048V (LTC1655), 1.25V (LTC1655L). There is a gain of
two from this pin to the output. The reference can be
overdriven from 2.2V to V
CC
/2 (LTC1655) and 1.3V to
V
CC
/2 (LTC1655L). When tied to V
CC
/2, the output will
swing from GND to V
CC
. The output can only swing to
within its offset specification of V
CC
(see Applications
Information).
V
OUT
(Pin 7): Deglitched Rail-to-Rail Voltage Output. V
OUT
clears to 0V on power-up.
V
CC
(Pin 8): Positive Supply Input. 4.5V ≤ V
CC
≤ 5.5V
(LTC1655), 2.7V ≤ V
CC
≤ 5.5V (LTC1655L). Requires a
0.1µF bypass capacitor to ground.
TI I G DIAGRA
WU W
D15
MSB
D14 D13 D1
t
1
t
6
D0
LSB
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1655/55L TD
D15
PREVIOUS WORD
D14
PREVIOUS WORD
D0
PREVIOUS WORD
D15
CURRENT WORD
D13
PREVIOUS WORD
t
9
t
7
12 3
15 16