Datasheet

7
LTC1650
CS/LD (Pin 8): The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the CLK
signal is enabled so the data can be clocked in. When
CS/LD is pulled high, data is loaded from the shift register
into the DAC register, updating the DAC output.
CLR (Pin 9): The DAC is cleared to V
RST
when this pin is
pulled low. It should be logic high for normal operation.
RSTOUT (Pin 10): The logic output pin that goes active
when any of the supplies drop below 2.5V. This pin is
active low.
REFHI (Pin 11): The Reference Input Pin. The DAC is
capable of 4-quadrant multiplying; this pin can swing
from 4.5V to –4V.
REFLO F/REFLO S (Pins 12, 13): The Force and Sense Pin
for the Lower Reference Input. This should nominally be
tied to ground. This pin can swing from –1V to 1V.
AV
SS
(Pin 14): The Analog Negative Supply Input. –5.25V
≤ AV
SS
≤ – 4.75V. Requires a bypass capacitor to ground.
AV
DD
(Pin 15): The Analog Positive Supply Input. 4.75V
≤ AV
DD
≤ 5.25V. Requires a bypass capacitor to ground.
UNI/BIP (Pin 16): The Unipolar/Bipolar Selection Pin. For
unipolar operation, tie this pin to V
OUT
and for bipolar
operation, tie this pin the REFHI.
CLK
t
1
D
IN
CS/LD
D
OUT
B14B15
B14 B13 B1
B0
LSB
B15
MSB
B13 B0B1
1650 TD
(PREVIOUS
WORD)
t
9
t
8
t
6
t
7
t
4
t
3
t
5
t
2
UU
U
PI FU CTIO S
TI I G DIAGRA
UWW