Datasheet

14
LTC1645
1645fa
An external hard reset is initiated at time point 6. The ON
pin is forced below 0.8V but above 0.4V, and the GATE n
pin voltages start to ramp down. V
OUT n
also starts to ramp
down, and RESET goes low when V
OUT2
drops below the
power-good trip level at time point 7.
Time points 8 to 15 are similar to time points 1 to 7, except
the ON pin’s different voltage thresholds are used to ramp
V
OUT1
and V
OUT2
separately. At time point 8, the ON pin
goes above 0.8V but below 2V, and one timing cycle later
(time point 9) GATE1 begins to ramp up with V
OUT1
following one gate-to-source voltage drop lower. At time
point 10, the ON pin goes above 2V and GATE2 immedi-
ately begins ramping up with V
OUT2
following one gate-to-
source voltage drop lower. As soon as V
OUT2
reaches its
power-good trip level at time point 11, a timing cycle
starts. At the end of the timing cycle (time point 12),
RESET goes high and the power-up process is complete.
The ON pin is forced below 2V but above 0.8V at time point
13 and the GATE2 pin voltage starts to ramp down. V
OUT2
also starts to ramp down and RESET goes low when V
OUT2
drops below the power-good trip level at time point 14.
When the ON pin goes below 0.8V but above 0.4V at time
point 15, GATE1 and V
OUT1
ramp down.
Time points 16 to 19 show the same power-up sequence
as time points 2 to 5, while time point 20 demonstrates the
GATE n pins being pulled immediately to ground (instead
of ramping down) by the ON pin going below 0.4V.
Power Supply Tracking and Sequencing Applications
The LTC1645 is able to sequence V
OUT n
in a number of
ways, including ramping V
OUT1
up first and down last;
ramping V
OUT1
up first and down first; ramping V
OUT1
up
first and V
OUT1
and V
OUT2
down together; and ramping
V
OUT1
and V
OUT2
up and down together.
Figure 15 shows an application ramping V
OUT1
and V
OUT2
up and down together. The ON pin must reach 0.8V to
ramp up V
OUT1
and V
OUT2
. The spare comparator pulls the
ON pin low until V
CC2
is above 2.3V, and the ON pin cannot
reach 0.8V before V
CC1
is above 3V. Thus, both input
supplies must be within regulation before a timing cycle
can start. At the end of the timing cycle, the output voltages
ramp up together. If either input supply falls out of
regulation, the gates of Q1 and Q2 are pulled low together.
Figure 16 shows an oscilloscope photo of the circuit in
Figure 15.
APPLICATIO S I FOR ATIO
WUUU
Figure 15. Ramping 3.3V and 2.5V Up and Down Together
Q1
1/2 Si4920DY
Q2
1/2 Si4920DY
0.01Ω*
0.01Ω*
10Ω
10Ω
1.18k
1%
10k
1.37k
1%
0.1µF
25V
0.33µF
*WSL1206-01-1% (VISHAY DALE)
C
LOAD1
C
LOAD2
D1
1N4002
D3
MBR0530T1
D2
1N4002
1
2
3
8
9
6
5
11
7
13 1214
BOTH CURRENT LIMITS: 5A
10
4
V
CC1
ON
FAULT
TIMER GND
SENSE1 GATE2GATE1
V
CC2
TRIP
POINT:
3V
V
IN1
3.3V
V
IN2
2.5V
V
OUT1
3.3V
2.5A
V
OUT2
2.5V
2.5A
µP RESET
LTC1645
(14-LEAD)
COMP
+
COMPOUT
FB
SENSE2
1645 F15
RESET
+
+
1.18k
1%
4.99k
1%
10k
1.37k
1%
1.82k
1%