Datasheet

LTC1644
13
1644f
APPLICATIO S I FOR ATIO
WUU
U
Figure 3. Normal Power-Down Sequence
Figure 2. Normal Power-Up Sequence
TIMER
During a power-up sequence, a 21µA current source is
connected to the TIMER pin (Pin 4) and current limit faults
are ignored until the voltage ramps to within 1V of 12V
IN
(Pin 1). This feature allows the chip to power up CPCI
boards with widely varying capacitive loads on the sup-
plies. The power-up time for any one of the four outputs is
given by Equation 2:
tXV
CXV
II
ON OUT
LOAD XVOUT OUT
LIMIT XVOUT LOAD XVOUT
()
=•
•
−






2
()
() ()
(2)
where XV
OUT
= 5V
OUT
, 3V
OUT
, 12V
OUT
or V
EEOUT
(–12V).
For example, for C
LOAD(5VOUT)
= 2000µF, I
LIMIT(5VOUT)
=
7A and I
LOAD(5VOUT)
= 5A, the 5V
OUT
turn-on time will be
~10ms. By substituting the variables in Equation 2 with the
appropriate values, the turn-on time for the other three
outputs can be calculated.
The timer period should be set longer than the maximum
supply turn-on time but short enough to not exceed the
maximum safe operating area of the pass transistor during
a short circuit. The timer period for the LTC1644 is given
by:
t
CV
A
TIMER
TIMER
=
•
µ
11
21
(3)
As a design aid, the timer period as a function of the timing
capacitor using standard values from 0.01µF to 1µF is
shown in Table 2.
TIMER
10V/DIV
GATE
5V/DIV
12V
OUT
10V/DIV
V
EEOUT
10V/DIV
5V
OUT
10V/DIV
3V
OUT
10V/DIV
LOCAL_PCI_RST#
5V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
PRECHARGE
5V/DIV
10ms/DIV
1644 F02
TIMER
10V/DIV
GATE
5V/DIV
12V
OUT
10V/DIV
V
EEOUT
10V/DIV
5V
OUT
10V/DIV
3V
OUT
10V/DIV
LOCAL_PCI_RST#
5V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
PRECHARGE
5V/DIV
10ms/DIV
1644 F03