Datasheet

7
LTC1627
load slightly allows constant frequency PWM operation
to resume.
Frequency synchronization is inhibited when the feedback
voltage V
FB
is below 0.6V. This prevents the external clock
from interfering with the frequency foldback for short-
circuit protection.
Dropout Operation
When the input supply voltage decreases toward the out-
put voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces the
main switch to remain on for more than one cycle until it
reaches 100% duty cycle. The output voltage will then be
determined by the input voltage minus the voltage drop
across the P-channel MOSFET and the inductor.
In Burst Mode operation or pulse skipping mode operation
(externally synchronized) with the output lightly loaded,
the LTC1627 transitions through continuous mode as it
enters dropout.
Undervoltage Lockout
A precision undervoltage lockout shuts down the LTC1627
when V
IN
drops below 2.5V, making it ideal for single
lithium-ion battery applications. In lockout, the LTC1627
draws only several microamperes, which is low enough to
prevent deep discharge and possible damage to the lithium-
ion battery nearing its end of charge. A 150mV hysteresis
ensures reliable operation with noisy supplies.
Low Supply Operation
The LTC1627 is designed to operate down to 2.65V supply
voltage. At this voltage the converter is most likely to be
running at high duty cycles or in dropout where the main
switch is on continuously. Hence, the I
2
R loss is due
mainly to the R
DS(ON)
of the P-channel MOSFET. See
Efficiency Considerations in the Applications Information
section.
When V
IN
is low (<4.5V) the R
DS(ON)
of the P-channel
MOSFET can be lowered by driving its gate below ground.
The top P-channel MOSFET driver makes use of a floating
return pin, V
DR
, to allow biasing below GND. A simple
charge pump bootstrapped to the SW pin realizes a
negative voltage at the V
DR
pin as shown in Figure 2. Using
Figure 3. Maximum Inductor Peak Current vs Duty Cycle
L1
C
OUT
100µF
V
OUT
1627 F02
V
IN
< 4.5V
D1
D2
C1
0.1µF
C2
0.1µF
V
DR
V
IN
SW
LTC1627
+
0
10 20
30
40
50
60
70 80
90 100
950
900
850
800
750
700
650
600
550
500
DUTY CYCLE (%)
1627 F03
MAXIMUM INDUCTOR PEAK CURRENT (mA)
WORST CASE
EXTERNAL
CLOCK SYNC
WITHOUT
EXTERNAL
CLOCK SYNC
V
IN
= 5V
Figure 2. Using a Charge Pump to Bias V
DR
the charge pump at V
IN
4.5V is not recommended to
ensure that (V
IN
– V
DR
) does not exceed its absolute
maximum voltage.
When V
IN
decreases to a voltage close to V
OUT
, the loop
may enter dropout and attempt to turn on the P-channel
MOSFET continuously. When the V
DR
charge pump is
enabled, a dropout detector counts the number of oscilla-
tor cycles that the P-channel MOSFET remains on, and
periodically forces a brief off period to allow C1 to
recharge. 100% duty cycle is allowed when V
DR
is grounded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability by preventing
subharmonic oscillations. It works by internally adding a
ramp to the inductor current signal at duty cycles in excess
of 40%. As a result, the maximum inductor peak current
is lower for V
OUT
/V
IN
> 0.4 than when V
OUT
/V
IN
< 0.4. See
the inductor peak current as a function of duty cycle graph
in Figure 3. The worst-case peak current reduction occurs
with the oscillator synchronized at its minimum frequency,
i.e., to a clock just above the oscillator free-running
OPERATIO
U