Datasheet

10
LTC1627
Auxiliary Winding Control Using SYNC/FCB Pin
The SYNC/FCB pin can be used as a secondary feedback
input to provide a means of regulating a flyback winding
output. When this pin drops below its ground referenced
0.8V threshold, continuous mode operation is forced. In
continuous mode, the main and synchronous MOSFETs
are switched continuously regardless of the load on the
main output.
Synchronous switching removes the normal limitation
that power must be drawn from the inductor primary
winding in order to extract power from auxiliary windings.
With continuous synchronous operation power can be
drawn from the auxiliary windings without regard to the
primary output load.
The secondary output voltage is set by the turns ratio of the
transformer in conjunction with a pair of external resistors
returned to the SYNC/FCB pin as shown in Figure 6. The
secondary regulated voltage V
SEC
in Figure 6 is given by:
VNVV V
R
R
SEC OUT DIODE
≅+
()( )
−>+
1081
4
3
.
where N is the turns ratio of the transformer, V
OUT
is the
main output voltage sensed by V
FB
and V
DIODE
is the
voltage drop across the Schottky diode.
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1627 circuits: V
IN
quiescent current and I
2
R
losses.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger
than the DC bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches R
SW
and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into SW pin from L is a function of
both top and bottom MOSFET R
DS(ON)
and the duty
cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative losses,
MOSFET switching losses and inductor core losses generally
account for less than 2% total additional loss.
Figure 6. Secondary Output Loop Connection
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
1µF
1627 F06
R4
R3
C
OUT
V
OUT
V
SEC
L1
1:N
+
+
SYNC/FCB
SW
LTC1627
APPLICATIO S I FOR ATIO
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