Datasheet

8
LTC1609
1609fa
16-BIT CAPACITIVE DAC
COMPREF BUF
2.5V REF
CAP
(2.5V)
C
SAMPLE
C
SAMPLE
DATA
DATACLK
SYNC
BUSY
CONTROL LOGIC
R/C PWRD SB/BTC EXT/INT TAG
INTERNAL
CLOCK
CS
ZEROING SWITCHES
V
DIG
V
ANA
R1
IN
R2
IN
R3
IN
REF
AGND1
AGND2
DGND
1609 BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER
SERIAL INTERFACE
4k
20k
10k
5k
20k
FUNCTIONAL BLOCK DIAGRA
UU
W
APPLICATIO S I FOR ATIO
WUUU
Conversion Details
The LTC1609 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit serial output. The ADC is complete
with a precision reference and an internal clock. The
control logic provides easy interface to microprocessors
and DSPs. (Please refer to the Digital Interface section for
timing information.)
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion the successive approximation
register (SAR) is reset. Once a conversion cycle has begun
it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, V
IN
is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
and the comparator offset is nulled by the autozero switches.
In this acquire phase, a minimum delay of 2µs will provide
enough time for the sample-and-hold capacitor to acquire
the analog signal. During the convert phase, the autozero
switches open, putting the comparator into the compare
mode. The input switch switches C
SAMPLE
to ground,
injecting the analog input charge onto the summing junc-
tion. This input charge is successively compared with the
binary-weighted charges supplied by the capacitive DAC.
Bit decisions are made by the high speed comparator. At
V
DAC
1609 F01
+
–
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
16-BIT
SHIFT REGISTER
COMPARATOR
SAMPLE
SI
R
IN2
R
IN1
V
IN
Figure 1. LTC1609 Simplified Equivalent Circuit