Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 20

LTC1609

1609fa

External Clock Mode

With the EXT/INT pin tied high, the DATACLK pin becomes

a digital input and the LTC1609 can accept an externally

supplied data clock. There are several ways in which the

conversion results can be clocked out. The data can be

clocked out during or after a conversion with a continuous

or discontinuous data clock. Figures 9 to 12 show the

timing diagram for each of these methods.

External Discontinuous Data Clock Data Read

After the Conversion

Figure 9 shows how the result from the current conver-

sion can be read out after the conversion has been

completed. The externally supplied data clock is running

discontinuously. R/C is used to initiate a conversion with

CS tied low. The conversion starts on the falling edge of

R/C. R/C should be returned high within 1.2µs to prevent

the transition from disturbing the conversion. After the

conversion has been completed (BUSY returning high), a

pulse on the SYNC pin will be generated on the rising edge

of DATACLK #0. The SYNC output can be captured on the

falling edge of DATACLK #0 or on the rising edge of

DATACLK #1. After the rising edge of DATACLK #1, the

SYNC output will go low and the MSB will be clocked out

on the DATA pin. This bit can be latched on the falling edge

of DATACLK #1 or on the rising edge of DATACLK #2. The

LSB will be valid on the falling edge of DATACLK #16 or the

rising edge of DATACLK #17. After the rising edge of

DATACLK #17 the DATA pin will take on the value of the

TAG pin that occurred at the rising edge of DATACLK #1.

A minimum of 17 clock pulses are required if the data is

captured on falling clock edges.

Using the highest frequency permitted for DATACLK

(20MHz), shifting the data out after the conversion will

not degrade the 200kHz throughput. This method mini-

mizes the possible external disturbances that can occur

while a conversion is in progress and will yield the best

performance.

APPLICATIO S I FOR ATIO

WUUU

Figure 9. Conversion and Read Timing Using an External Discontinuous Data Clock

(EXT/INT Tied High, CS Tied Low). Read Conversion Result After the Conversion

0123 151617

TAG0TAG

DATA

SYNC

BUSY

R/C

EXTERNAL

DATACLK

TAG1 TAG2 TAG3 TAG15

B1B14 B13

B15

(MSB)

B0 TAG0 TAG1 TAG2

TAG16 TAG17 TAG18 TAG19

1606 F09