Datasheet
7
LTC1608
UU
W
FU CTIO AL BLOCK DIAGRA
Load Circuits for Access Timing
Load Circuits for Output Float Delay
1k
(A) Hi-Z TO V
OH
AND V
OL
TO V
OH
C
L
1k
5V
DNDN
(B) Hi-Z TO V
OL
AND V
OH
TO V
OL
C
L
1608 TC01
1k
(A) V
OH
TO Hi-Z
C
L
1k
5V
DNDN
(B) V
OL
TO Hi-Z
C
L
1608 TC02
TEST CIRCUITS
2.2µF
10µF
10µF
10Ω
22µF
4
6
DIFFERENTIAL
ANALOG INPUT
±2.5V
REFCOMP
4.375V
CONTROL
LOGIC
AND
TIMING
B15 TO B0
16-BIT
SAMPLING
ADC
–
+
10µF
5V OR
3V
µP
CONTROL
LINES
D15 TO D0
OUTPUT
BUFFERS
16-BIT
PARALLEL
BUS
11 TO 26
1608 BD
OGND
OV
DD
28
29
1
2
A
IN
+
A
IN
–
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
7.5k
3
36
35
10
9
5V
5V
AV
DD
AV
DD
DV
DD
DGND
V
REF
8
AGND
AGND
7
AGND
5
AGND
34
–5V
V
SS
10µF
2.5V
REF
10µF
1.75X
+
+
+ +
+
+
APPLICATIO S I FOR ATIO
WUUU
CONVERSION DETAILS
The LTC1608 uses a successive approximation algorithm
and internal sample-and-hold circuit to convert an analog
signal to a 16-bit parallel output. The ADC is complete with
a sample-and-hold, a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) resets. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the A
IN
+
and A
IN
–
inputs are
acquired during the acquire phase and the comparator
offset is nulled by the zeroing switches. In this acquire
phase, a duration of 480ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase, the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
SMPL
capacitors to ground,
transferring the differential analog input charge onto the
summing junctions. This input charge is successively