Datasheet

11
LTC1608
RD = CONVST
CS = 0
BUSY
1608 F08
t
CONV
t
6
DATA (N – 1)
D15 TO D0
DATA
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
DATA N
D15 TO D0
t
11
t
8
t
10
t
7
RD = CONVST
BUSY
CS = 0
1608 F09
t
CONV
t
6
DATA (N – 1)
D15 TO D0
DATA
DATA N
D15 TO D0
t
10
t
11
t
8
Figure 8. Mode 2. Slow Memory Mode Timing
Figure 9. ROM Mode Timing
APPLICATIO S I FOR ATIO
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spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1608
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (settling time must be 200ns for full throughput
rate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (<100Ω) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
Figure 10. t
ACQ
vs Source Resistance
SOURCE RESISTANCE (Ω)
1 10 100 1k 10k
ACQUISITION TIME (µs)
10
1
0.1
0.01
1608 F10
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 15MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.