Datasheet

8
LTC1606
1606fa
Conversion Details
The LTC1606 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit or two byte parallel output. The
ADC is complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, V
IN
is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
and the comparator offset is nulled by the autozero switches.
In this acquire phase, a minimum delay of 1.5µs will
provide enough time for the sample-and-hold capacitor to
acquire the analog signal. During the convert phase, the
autozero switches open, putting the comparator into the
compare mode. The input switch switches C
SAMPLE
to
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the V
IN
input charge. The SAR contents (a 16-bit
data word) that represents the V
IN
are loaded into the
16-bit output latches.
Driving the Analog Inputs
The nominal input range for the LTC1606 is ±10V or
(±4 • V
REF
) and the input is overvoltage protected to ±25V.
The input impedance is typically 10kΩ, therefore, it should
be driven with a low impedance source. Wideband noise
coupling into the input can be minimized by placing a
1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
Load Circuit for Access Timing
1k 30pF 30pF
DBN
DBN
1k
5V
1606 TC01
A. Hi-Z TO V
OH
AND V
OL
TO V
OH
B. Hi-Z TO V
OL
AND V
OH
TO V
OL
Load Circuit for Output Float Delay
1k 30pF 30pF
DBN
DBN
1k
5V
1606 TC02
A. V
OH
TO Hi-Z B. V
OL
TO Hi-Z
TEST CIRCUITS
APPLICATIO S I FOR ATIO
WUUU
V
DAC
1606 • F01
+
–
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
16-BIT
LATCH
COMPARATOR
SAMPLE
SI
R
IN2
R
IN1
V
IN
Figure 1. LTC1606 Simplified Equivalent Circuit
1606 • F02
1000pF 33.2k LTC1606
V
IN
CAP
A
IN
200Ω
Figure 2. Analog Input Filtering