Datasheet

1603f
7
LTC1603
UU
W
FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
1k
(A) Hi-Z TO V
OH
AND V
OL
TO V
OH
C
L
1k
5V
DNDN
(B) Hi-Z TO V
OL
AND V
OH
TO V
OL
C
L
1603 TC01
1k
(A) V
OH
TO Hi-Z
C
L
1k
5V
DNDN
(B) V
OL
TO Hi-Z
C
L
1603 TC02
2.2µF
10µF
10µF
10Ω
47µF
4
6
DIFFERENTIAL
ANALOG INPUT
±2.5V
REFCOMP
4.375V
CONTROL
LOGIC
AND
TIMING
B15 TO B0
16-BIT
SAMPLING
ADC
–
+
10µF
5V OR
3V
µP
CONTROL
LINES
D15 TO D0
OUTPUT
BUFFERS
16-BIT
PARALLEL
BUS
11 TO 26
1603 TA01
OGND
OV
DD
28
29
1
2
A
IN
+
A
IN
–
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
7.5k
3
36
35
10
9
5V
5V
AV
DD
AV
DD
DV
DD
DGND
V
REF
8
AGND
AGND
7
AGND
5
AGND
34
–5V
V
SS
10µF
2.5V
REF
10µF
1.75X
+
+
+ +
+
+