Datasheet

11
LTC1591/LTC1597
15917fa
Table 1
CONTROL INPUTS
CLR WR LD REGISTER OPERATION
0 X X Reset Input and DAC Register to All 0s for LTC1591/LTC1597 and Midscale for LTC1591-1/LTC1597-1 (Asynchronous Operation)
1 0 0 Load Input Register with All 14/16 Data Bits
1 1 1 Load DAC Register with the Contents of the Input Register
1 0 1 Input and DAC Register Are Transparent
1 CLK = LD and WR Tied Together. The 14/16 Data Bits Are Loaded into the Input Register on the Falling Edge of the CLK and Then
Loaded into the DAC Register on the Rising Edge of the CLK
1 1 0 No Register Operation
TRUTH TABLE
BLOCK DIAGRA SM
W
LTC1591
96k
12k
12k
96k
48k
96k
48k
96k
DECODER
D13
(MSB)
D11
D12
D13
D10 D9 D0
(LSB)
LOAD
V
CC
REF R
FB
I
OUT1
AGND
CLR
28
DGND
22
1591 BD
DAC REGISTER
48k 48k 48k 48k 48k 48k 48k
12k
8
23
R1
3
R
COM
2
1
LD
9
10
D12
11
D2
21
D1
24
D0
25
NC
27
NC
26
WR
7
6
5
R
OFS
4
• • •
12k
WR
INPUT REGISTER
• • • •
RST
RST